PS081 datasheet(77/155 Pages) AMSCO

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4-20

PSØ81

4.5.2

SPI Timing

Here we describe only the SPI timing for operation as a pure converter that communicates with an

external microcontroller. PSØ81 supports only 1 mode out of 4 possible ones:

Clock Phase Bit = 1, Clock Polarity Bit = 0

Data transfer with the falling edge of the clock. The clock starts from low.

Figure 4.13 SPI timing

Table 4.4 SPI Timings

Time:

Description:

min [ns]

tpwssn

Pulse width SSN

500

tsussn

Setup time SSN / SCK

500

tpwh

Pulse width SCK high

500

tpwl

Pulse width SCK low

500

tsud

Setup time data

thd

Hold time data

tpwh and tpwl together define the clock frequency of the SPI interface. Consequently, 1µs corres-

ponds to a clock rate of 1 MHz to run the SPI transmission. After sending a reset through the SPI,

it is necessary to wait for 200 µs before sending the next opcode. If auto-configuration is on, it is

necessary to wait for 1 ms. After writing to the RAM via SPI it is necessary to wait for 10 µs.

4.5.3

SPI - Instructions

4.5.3.1

RAM Access

RAM Write

= b00000000

= h00

RAM Read

= b01000000

= h40

New_LCD

= b01000110

= h46

Power reset

= b11110000

= hF0

Init reset

= b11000000

= hC0

Start_new_cycle = b11001100

= hCC

(continuous)

Start_TDC_cycle = b11001110

= hCE

(single conversion)

watch_dog_off

= b10011110

= h9E

watch_dog_on

= b10011111

= h9F

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