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WM5102 Datasheet(PDF) 159 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 159 Page - Wolfson Microelectronics plc |
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159 / 334 page ![]() Production Data WM5102 w PD, June 2014, Rev 4.2 159 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1056 (0420h) Output Path Config 3L 15:14 DAC3_FREQ_RA NGE_LIM [1:0] 00 Output Path 3 Clocking Frequency Limit When OUT3_OSR=0 00 = 3.072MHz (2.8224MHz) 01 = 6.144MHz (5.6448MHz) 10 = 12.288MHz (11.2896MHz) 11 = Reserved When OUT3_OSR=1 00 = 6.144MHz (5.6448MHz) 01 = 6.144MHz (5.6448MHz) 10 = 12.288MHz (11.2896MHz) 11 = Reserved Note that the Clocking Frequency will be <= SYSCLK under all register settings. The frequencies in brackets apply for 44.1kHz-related sample rates only (ie. SAMPLE_RATE_n = 01XXX). 13 OUT3_OSR 0 Output Path 3 Oversample Rate 0 = Normal mode 1 = High Performance mode R1064 (0428h) Output Path Config 4L 13 OUT4_OSR 0 Output Path 4 Oversample Rate 0 = Normal mode 1 = High Performance mode R1072 (0430h) Output Path Config 5L 13 OUT5_OSR 0 Output Path 5 Oversample Rate 0 = Normal mode 1 = High Performance mode Table 63 Output Signal Path Control |
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