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WM5102 Datasheet(PDF) 157 Page - Wolfson Microelectronics plc

Part # WM5102
Description  Audio Hub CODEC with Voice Processor DSP
PDF  334 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM5102 Datasheet(HTML) 157 Page - Wolfson Microelectronics plc

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Production Data
WM5102
w
PD, June 2014, Rev 4.2
157
OUTPUT SIGNAL PATH CONTROL
Under default register conditions, the output paths are configured for optimum power consumption.
Audio performance can be improved using the register bits defined in Table 63, but power
consumption is also increased.
A high performance mode can be selected on the output signal paths by setting the _OSR bits for the
respective paths. When the OUTn_OSR bit is set, the audio performance is improved, but power
consumption is also increased.
The DAC clocking frequency for outputs paths OUT1, OUT2 and OUT3 can be controlled using the
DACn_FREQ_LIM registers. Under normal operating conditions, the 6.144MHz (or 5.6448MHz) clock
frequency is used. Under specific signal conditions, the use of higher clock frequencies can improve
the noise performance. Note that the DACn_FREQ_LIM registers select the upper frequency limit; the
actual clock frequency is controlled dynamically according to the signal conditions.
The recommended options for configuring the Headphone output paths (OUT1 and OUT2) are noted
in Table 60.
DESCRIPTION
OUT1_OSR,
OUT2_OSR
DAC1_FREQ_LIM,
DAC2_FREQ_LIM
Low Power (default)
0
00
Normal operation
1
01
High Performance
1
10
Table 60 Headphone Output Control
The recommended options for configuring the Earpiece output path (OUT3) are noted in Table 61.
DESCRIPTION
OUT3_OSR
DAC3_FREQ_LIM
Low Power (default)
0
00
Normal operation
1
01
Table 61 Earpiece Output Control
The SPKCLK frequency of the PDM output path (OUT5) is controlled by the OUT5_OSR register, as
described in Table 62. When the OUT5_OSR bit is set, the audio performance is improved, but power
consumption is also increased.
Note that the SPKCLK frequencies noted in Table 62 assume that the SYSCLK frequency is a
multiple of 6.144MHz (SYSCLK_FRAC=0). If the SYSCLK frequency is a multiple of 5.6448MHz
(SYSCLK_FRAC=1), then the SPKCLK frequencies will be scaled accordingly.
CONDITION
SPKCLK FREQUENCY
OUT5_OSR = 0
3.072MHz
OUT5_OSR = 1
6.144MHz
Table 62 SPKCLK Frequency



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