WM5102 datasheet(273/334 Pages) WOLFSON

273 / 334 page

Production Data

WM5102

PD, June 2014, Rev 4.2

273

POWER-ON RESET (POR) AND HARDWARE RESET

The WM5102 will remain in the reset state until AVDD, DBVDD1 and DCVDD are all above their

respective reset thresholds. Note that specified device performance is not assured outside the voltage

ranges defined in the “Recommended Operating Conditions” section.

The RESET

¯¯¯¯¯¯ input must be asserted (logic 0) during power-up, and held asserted until after the AVDD,

DBVDD1 and DCVDD supplies are within the recommended operating limits. If DCVDD is powered

from internal LDO, then the DCVDD supply must be enabled using the LDOENA pin, and the RESET

¯¯¯¯¯¯

pin held asserted until at least 1.5ms after the LDO has been enabled.

Refer to “Recommended Operating Conditions” for the WM5102 power-up sequencing requirements.

If DCVDD is powered from LDO1, then the DCVDD supply must be enabled using the LDOENA pin

for the initial power-up. Note that subsequent interruption to DCVDD should only be permitted as part

of a control sequence for entering Sleep mode.

After the initial power-up, the Power-On Reset will be re-scheduled following an interruption to the

DBVDD1 or AVDD supplies. Note that the AVDD supply must always be maintained whenever the

DCVDD supply is present.

The WM5102 provides a Hardware Reset function, which is executed whenever the RESET

¯¯¯¯¯¯ input is

asserted (logic 0). The RESET

¯¯¯¯¯¯ input is active low and is referenced to the DBVDD1 power domain.

A Hardware Reset causes most of the WM5102 control registers to be reset to their default states.

Note that the Control Write Sequencer memory and DSP firmware memory contents are retained

during Hardware Reset - provided DCVDD is held above its reset threshold.

See the “Applications Information” section for a summary of the WM5102 memory reset conditions.

If DCVDD is powered from LDO1, it is recommended that the LDOENA pin is asserted (logic 1) before

the Hardware Reset; this ensures the Write Sequencer and DSP memory contents are retained, and

also allows faster reset time. If LDOENA is not asserted prior to the reset, then LDO1 will be disabled,

and the power-up requirements described above must be followed.

If the WM5102 SLIMbus component is in its operational state, then it must be reset prior to scheduling

a Hardware Reset or Power-On Reset. See “SLIMbus Interface Control” for details of the SLIMbus

reset control messages.

An internal pull-up resistor is enabled by default on the RESET

¯¯¯¯¯¯ pin; this can be configured using the

RESET_PU register bit described in Table 122.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3104

(0C20h)

Misc Pad

Ctrl 1

RESET_PU

RESET Pull-up enable

0 = Disabled

1 = Enabled

Table 122 Reset Pull-Up Configuration

WM5102 Datasheet(PDF) 273 Page - Wolfson Microelectronics plc

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