WM5102 datasheet(274/334 Pages) WOLFSON

274 / 334 page

WM5102

Production Data

PD, June 2014, Rev 4.2

274

Following Power-On Reset (POR), Hardware Reset or Software Reset, a Boot Sequence is executed.

The BOOT_DONE_STS register is asserted on completion of the Boot Sequence, as described in

Table 123. Control register writes should not be attempted until the BOOT_DONE_STS register has

been asserted.

The BOOT_DONE_STS signal is an input to the Interrupt control circuit and can be used to trigger an

Interrupt event - see “Interrupts”. Under default register conditions, (including following POR,

Hardware Reset or Software Reset), a falling edge on the IRQ

¯¯¯ pin will indicate completion of the Boot

Sequence.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3363

(0D23h)

Interrupt

Raw

Status 5

BOOT_DONE_S

Boot Status

0 = Busy (boot sequence in progress)

1 = Idle (boot sequence completed)

Control register writes should not be

attempted until Boot Sequence has

completed.

Table 123 Device Boot-Up Status

Following Power-On Reset (POR), Hardware Reset, Software Reset, or Wake-Up (from Sleep mode),

a sequence of device initialisation writes must be executed, as detailed in Table 124.

The host system should ensure that the WM5102 is ready before attempting these (or any other)

Control Register writes.

In the case of Power-On Reset (POR), Hardware Reset or Software Reset, the initialisation settings

should be written after the BOOT_DONE_STS bit has been asserted (also indicated by a falling edge

of the IRQ

¯¯¯ pin).

In the case of Wake-Up (from Sleep mode), then at least 1.5ms must be allowed from the Wake-Up

event before writing to any Control Registers. Note that, in a typical implementation, the Interrupt

circuit is configured to provide indication of the Wake-Up event.

WM5102 INITIALISATION

Write 0x0001 to Register R25 (0x0019)

Write 0xE022 to Register R129 (0x0081)

Write 0x0000 to Register R724 (0x02D4)

Write 0x000C to Register R862 (0x035E)

Write 0xDC1A to Register R1091 (0x0443)

Write 0x0066 to Register R1200 (0x04B0

Write 0x0001 to Register R1307 (0x051B)

Write 0x0001 to Register R1371 (0x055B)

Write 0x0001 to Register R1435 (0x059B)

Table 124 Device Initialisation Register Settings

The WM5102 is in Sleep mode when AVDD and DBVDD1 are present, and DCVDD is below its reset

threshold. (Note that specific control requirements are also applicable for entering Sleep mode, as

described in “Low Power Sleep Configuration”.)

In Sleep mode, most of the Digital Core (and control registers) are held in reset; selected functions

and control registers are maintained via an ‘Always-On’ internal supply domain. See “Low Power

Sleep Configuration” for details of the ‘Always-On’ functions.

See “Software Reset, Wake-Up, and Device ID” for details of the Wake-Up transition (exit from Sleep

mode).

WM5102 Datasheet(PDF) 274 Page - Wolfson Microelectronics plc

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