WM5102 datasheet(277/334 Pages) WOLFSON

277 / 334 page

Production Data

WM5102

PD, June 2014, Rev 4.2

277

SOFTWARE RESET, WAKE-UP, AND DEVICE ID

A Software Reset is executed by writing any value to register R0. A Software Reset causes most of

the WM5102 control registers to be reset to their default states. Note that the Control Write Sequencer

memory and DSP firmware memory contents are retained during Software Reset.

A Wake-Up transition (from Sleep mode) is similar to a Software Reset, but selected functions and

control registers are maintained via an ‘Always-On’ internal supply domain. The ‘Always-On’ registers

are not reset during Wake-Up. See “Low Power Sleep Configuration” for details of the ‘Always-On’

functions.

The Control Write Sequencer and DSP Firmware memory contents are retained during Software

Reset - provided DCVDD is held above its reset threshold.

The Control Write Sequencer memory contents are retained during Sleep mode; the DSP memory

contents are reset during Sleep mode.

See the “Applications Information” section for a summary of the WM5102 memory reset conditions.

If DCVDD is powered from LDO1, it is recommended that the LDOENA pin is asserted (logic 1) before

a Software Reset; this ensures the Write Sequencer and DSP memory contents are retained, and also

allows faster reset time. If LDOENA is not asserted prior to the reset, then LDO1 will be disabled, and

the power-up sequencing requirements described in “Power-On Reset (POR) and Hardware Reset”

must be followed.

Following Power-On Reset (POR), Hardware Reset or Software Reset, a Boot Sequence is executed.

The BOOT_DONE_STS register (see Table 123) is de-asserted during any Reset, and is asserted on

completion of the boot-up sequence. Control register writes should not be attempted until the

BOOT_DONE_STS register has been asserted.

The BOOT_DONE_STS signal is an input to the Interrupt control circuit and can be used to trigger an

Interrupt event - see “Interrupts”.

Following Power-On Reset (POR), Hardware Reset, Software Reset, or Wake-Up (from Sleep mode),

a sequence of device initialisation writes must be executed, as detailed in Table 126.

The host system should ensure that the WM5102 is ready before attempting these (or any other)

Control Register writes.

In the case of Power-On Reset (POR), Hardware Reset or Software Reset, the initialisation settings

should be written after the BOOT_DONE_STS bit has been asserted (also indicated by a falling edge

of the IRQ

¯¯¯ pin).

In the case of Wake-Up (from Sleep mode), then at least 1.5ms must be allowed from the Wake-Up

event before writing to any Control Registers. Note that, in a typical implementation, the Interrupt

circuit is configured to provide indication of the Wake-Up event.

WM5102 INITIALISATION

Write 0x0001 to Register R25 (0x0019)

Write 0xE022 to Register R129 (0x0081)

Write 0x0000 to Register R724 (0x02D4)

Write 0x000C to Register R862 (0x035E)

Write 0xDC1A to Register R1091 (0x0443)

Write 0x0066 to Register R1200 (0x04B0

Write 0x0001 to Register R1307 (0x051B)

Write 0x0001 to Register R1371 (0x055B)

Write 0x0001 to Register R1435 (0x059B)

Table 126 Device Initialisation Register Settings

WM5102 Datasheet(PDF) 277 Page - Wolfson Microelectronics plc

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