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PM8313 Datasheet(PDF) 122 Page - PMC-Sierra, Inc

Part # PM8313
Description  M13 MULTIPLEXER
PDF  192 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM8313 Datasheet(HTML) 122 Page - PMC-Sierra, Inc

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PM8313 D3MX
DATA SHEET
PMC-920702
ISSUE 5
M13 MULTIPLEXER
112
IDLI:
The IDLI bit indicates that a change of state of the DS3 IDLE signal detector
has occurred. When the IDLI bit is a logic 1, a change in the IDLE detector
state has occurred. When the IDLI bit is logic 0, no change in the IDLE signal
detector state has occurred.
FERFI:
The FERFI bit indicates that a change of state of the FERF indication has
occurred. The FERF indication is visible in the FERFV bit location of the DS3
FRMR Status register and on the RFERF pin. When the FERFI bit is a logic
1, a change in the FERF state has occurred. When the FERFI bit is logic 0,
no change in the FERF state has occurred.
CBITI:
The CBITI bit indicates that a change of state in the C-bit Identification
indication internal to the DS3 FRMR has occurred. When the CBITI bit is a
logic 1, a change in the internal CBIT state has occurred. When the CBITI bit
is logic 0, no change in the CBIT state has occurred.
REDI:
The REDI bit indicates that a change of state of the DS3 RED indication has
occurred. The DS3 RED indication is visible in the REDV bit location of the
DS3 FRMR Status register and on the ROOF/RRED pin when the REDO bit
in the Master Alarm Enable register ( register 06Hex) is set to logic 1. When
the REDI bit is a logic 1, a change in the RED state has occurred. When the
REDI bit is logic 0, no change in the RED state has occurred.
COFAI:
The COFAI bit indicates that a change of frame alignment (i.e. a COFA event)
has occurred. When the COFAI bit is a logic 1, the frame alignment
acquisition circuitry has detected that the new alignment differs from the
previous frame alignment. When the COFAI bit is logic 0, there was no
difference from the current frame alignment and the previous frame
alignment.
The interrupt status bits are cleared when the FRMR Interrupt Status Register is
read.



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