PM8313 datasheet(131/192 Pages) PMC

131 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

121

Registers 44H, 54H, 64H, 74H, 84H, 94H and A4H: DS2 FRMR Monitor

Interrupt Enable/Status

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

Unused

Bit 4

Unused

Bit 3

Unused

Bit 2

R/W

INTE

Bit 1

INTR

Bit 0

OVR

INTE:

The interrupt enable (INTE) bit allows the DS2 FRMR to assert the INTB

output upon register transfers. A logic 1 in the INTE bit position enables the

DS2 FRMR to generate a microprocessor interrupt when the counter values

are transferred to the Holding Registers. A logic 0 in the INTE bit position

disables the DS2 FRMR from generating an interrupt. When the TSB is reset,

the INTE bit is set to logic 0, disabling the interrupt. The interrupt is cleared

when this register is read if its assertion was a result a transfer operation.

INTR:

The interrupt (INTR) bit indicates the current status of the internal interrupt

signal. A logic 1 in this bit position indicates that a transfer of counter values

to the Holding Registers has occurred; a logic 0 indicates that no transfer has

occurred. This bit is set to logic 0 when this register is read. The value of the

INTR bit is not affected by the value of the INTE bit.

OVR:

The overrun (OVR) bit indicates the overrun status of the Holding Registers.

A logic 1 in this bit position indicates that a previous interrupt has not been

cleared before the end of the next accumulation interval, and that the

contents of the Holding Registers have been overwritten. A logic 0 indicates

that no overrun has occurred. This bit is reset to logic 0 when this register is

read.

PM8313 Datasheet(PDF) 131 Page - PMC-Sierra, Inc

PM8313 Datasheet(HTML) 131 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL