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PM8313 Datasheet(PDF) 148 Page - PMC-Sierra, Inc

Part # PM8313
Description  M13 MULTIPLEXER
PDF  192 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM8313 Datasheet(HTML) 148 Page - PMC-Sierra, Inc

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PM8313 D3MX
DATA SHEET
PMC-920702
ISSUE 5
M13 MULTIPLEXER
138
Table 1
- Test Mode Address Locations – Read from Inputs
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10EH
TDLSIG/
TDLUDR3
TOH
TOHEN
120H
TDLEOMI
128H
TIMFP4
TICLK
134H
RNEG/
RLCV1,4
RPOS/
RDAT1,4
RCLK2
14AH
TD1DAT4
TD1DAT3
TD1DAT2
TD1DAT1
TD1CLK4
TD1CLK3
TD1CLK2
TD1CLK1
15AH
TD1DAT8
TD1DAT7
TD1DAT6
TD1DAT5
TD1CLK8
TD1CLK7
TD1CLK6
TD1CLK5
16AH
TD1DAT12
TD1DAT11
TD1DAT10
TD1DAT9
TD1CLK12
TD1CLK11
TD1CLK10
TD1CLK9
17AH
TD1DAT16
TD1DAT15
TD1DAT14
TD1DAT13
TD1CLK16
TD1CLK15
TD1CLK14
TD1CLK13
18AH
TD1DAT20
TD1DAT19
TD1DAT18
TD1DAT17
TD1CLK20
TD1CLK19
TD1CLK18
TD1CLK17
19AH
TD1DAT24
TD1DAT23
TD1DAT22
TD1DAT21
TD1CLK24
TD1CLK23
TD1CLK22
TD1CLK21
1AAH
TD1DAT28
TD1DAT27
TD1DAT26
TD1DAT25
TD1CLK28
TD1CLK27
TD1CLK26
TD1CLK25
Notes:
1. If the RINV and the DS3 FRMR UNI register bits are logic one, the values
read are active low.
2. If the RFALL register bit is a logic 1, the value read is inverted.
3. The TEXHDLC register bit must be a logic 1 to sense this input.
4. These inputs must be clocked by the VCLK_IOTST bit before being read.
This requires writing a logic 0 then a logic 1 to the VCLK_IOTST bit .
Writing the following address locations forces the outputs to the value in the
corresponding bit position:
Table 2
- Test Mode Address Locations – Write to Outputs
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10CH
TNEG/
TMFP1,3
TPOS/
TDAT2,3
TNEG/
TMFP2,3
TPOS
TDAT1,3/
TCLK4
10EH
TDLCLK/
TDLINT5
TOHFP
TOHCLK
110H
INTB7



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