PM8313 datasheet(152/192 Pages) PMC

152 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

142

5. If UDR=1, then clear the Status Register, clear the UDR bit (deassert the

TDLEOMI input and clear EOM, if set) in the XFDL Configuration Register to

logic 0. Restart the current frame.

In the case of interrupt driven data transfer, the TDLINT output of the XFDL is

connected to the interrupt input of the processor, and the interrupt service

routine should process the data exactly as described above for the polled mode.

The XFDL can also be used with a DMA controller to process the frame data. In

this case, the TDLUDR output is connected to the processor interrupt input. The

TDLINT output of the XFDL is connected to the DMA request input of the DMA

controller. The DMA "end" signal from the controller can be connected to the

TDLEOMI input. The DMA controller writes a data byte to the XFDL whenever

the TDLINT output is asserted. Upon writing the last byte of the packet to XFDL,

the DMA asserts the TDLEOMI input. Note that the TDLEOMI input is expected

to be "glitch-free" and, when pulsed high, sets the EOM register bit in the

transmitter configuration register. The EOM register bit is used by the transmitter

to determine the course of action when the current data byte is exhausted. If

there is a problem during transmission and an underrun condition occurs, then

the TDLUDR output goes high and the processor is interrupted. The processor

can then halt the DMA controller, clear the problem condition, reset the frame

data pointers, and restart the DMA controller to resend the data frame.

12.2

Using the Internal Data Link Receiver

On power up of the D3MX, the RFDL should be disabled by setting the EN bit in

the Configuration Register to logic 0. The Interrupt Control/Status Register

should then be initialized to select the FIFO buffer fill level at which an interrupt

will be generated.

After the Interrupt Control/Status Register has been written to, the RFDL can be

enabled at any time by setting the EN bit in the Configuration Register to logic 1.

When the RFDL is enabled, it will assume that the link status is idle (all ones)

and immediately begin searching for flags. When the first flag is found, an

interrupt will be generated (if enabled), and the byte received before the first flag

was detected will be written into the FIFO buffer. Because the FLG and EOMR

bits are passed through the buffer, this dummy write allows the Status Register to

accurately reflect the current state of the data link. A Status Register read after a

Data Register read of the dummy byte will return EOMR as logic 1 and FLG as

logic 1. The first interrupt and data byte read after the RFDL is enabled (or TR bit

set to logic 1) is an indication of the link status, and the data byte should

therefore be discarded. It is up to the controlling processor to keep track of the

PM8313 Datasheet(PDF) 152 Page - PMC-Sierra, Inc

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