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PM8313 Datasheet(PDF) 155 Page - PMC-Sierra, Inc |
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PM8313 Datasheet(HTML) 155 Page - PMC-Sierra, Inc |
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155 / 192 page  PM8313 D3MX DATA SHEET PMC-920702 ISSUE 5 M13 MULTIPLEXER 145 Figure 6 - Typical Data Frame TRANSMIT 8765432 1 0111111 0 FLAG Address (high) (low) CONTROL Frame Check Sequence (FCS) 0111111 0 FLAG BIT: data bytes received and transferred to the FIFO, bit 1 first data bytes written to the Transmit Data Register and serially transmitted, bit 1 first appended after EOM is set, if CRC is set RECEIVE Bit 1 is the first serial bit to be transmitted or received. Both the address and control bytes must be supplied by an external processor and are shown for reference purposes only. 12.2.1 Key used on subsequent diagrams: Flag - flag sequence (01111110) Abort - abort sequence (01111111) D1 - Dn - n frame data bytes R - remainder bits (less than 8) C1, C2 - CRC-CCITT information B1, B2, B3 - groupings of 8 bits |
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