PM8313 datasheet(151/192 Pages) PMC

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PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

141

OPERATION

12.1

Using the Internal Data Link Transmitter

Upon reset of the D3MX, the XFDL should be disabled by setting the EN bit in

the Configuration/Control Register to logic 0. If data is not ready to be

transmitted, the TDLINT output should also be masked by setting the INTE bit to

logic 0.

When a frame (or frames) of data are ready to be transmitted, the Configuration/

Control Register should be initialized for transmission: if the FCS is desired, the

CRC bit should be set to logic 1; if the block is to be used in interrupt driven

mode, interrupts should be enabled by setting the INTE bit to logic 1. Finally, the

XFDL can be enabled by setting the EN bit to logic 1.

The XFDL can be used in a polled, interrupt driven, or DMA-controlled mode for

the transfer of frame data. In the polled mode, the TDLINT and TDLUDR outputs

of the XFDL are not used, and the processor controlling the XFDL must

periodically read the Status Register to determine when to write to the Transmit

Data Register. In the interrupt driven mode, the processor controlling the XFDL

uses the TDLINT output to determine when to write to the Transmit Data

as a DMA request input to the DMA controller, and the TDLUDR output is used

as an interrupt to the processor to allow handling of exceptions.

If the XFDL data transfer is operating in the polled mode, then a timer

periodically starts up a service routine, which should process data as follows:

1. Read the XFDL Status Register and check the UDR and INTR bits.

2. If UDR=1, then clear the Status Register, set the UDR bit in the XFDL

Configuration Register to logic 0, and restart the current frame.

3. If INTR=1, then:

a) If there is still data to send, then write the next data byte to the Transmit

Data Register;

b) f all bytes in the frame have been sent, then set the EOM bit in the XFDL

Configuration Register to logic 1, and set the INTE bit to logic 0. Alternatively,

assert the TDLEOMI input.

4. Read the Status Register and check the UDR bit.

PM8313 Datasheet(PDF) 151 Page - PMC-Sierra, Inc