PM8313 datasheet(150/192 Pages) PMC

150 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

140

2. This bit only has effect if the TUNI register bit is logic zero.

3. These bits are only presented on the output after being clocked by the TCLK

output. This requires writing a logic 0 then a logic 1 to the TCLK bit .

4. The TCLK output is inverted if the TRISE bit is a logic 0.

5. This bit only has effect if the TEXHDLC register bit is logic 1.

6. This bit only has effect if the TEXHDLC register bit is logic 0. The polarity of

the signal forced on the output pin is determined by the state of the TINTPOL

and TUDRPOL register bits.

7. Writing a logic 1 to any INTB bit asserts the INTB output low.

8. This bit only has effect if the REXHDLC register bit is logic 1.

9. This bit only has effect if the REXHDLC register bit is logic 0. The polarity of

the signal forced on the output pin is determined by the state of the RINTPOL

and REOMPOL register bits.

The state of the configuration registers must be considered. To make board

testing more straight forward, it is recommended that the normal mode registers

be initialized to the following state:

Write register 02H with 00H

(Clears BYP[7:1])

Write register 03H with C0H

(Sets REXHDLC and TEXHDLC)

or with 0FH

(Sets REOMPOL,TUDRPOL,RINTPOL,

TINTPOL).

Write register 04H with 00H

(Clears LINEAIS[1:0], LLBE and DLBE.)

Write register 05H with 08H

(Sets TRISE. Clears TINV, TUNI, RINV,

RFALL.)

Write register 07H with 04H

(Sets IOTST to put device into test mode.)

Write register 34H with 00H

(Clears DS3 FRMR UNI bit.)

If the registers are in a different state than this, adjustments must be made for

inversion of assertion levels.

PM8313 Datasheet(PDF) 150 Page - PMC-Sierra, Inc