PM8313 datasheet(158/192 Pages) PMC

158 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

148

Figure 9

- XFDL Normal Data Sequence

Flag

CRC1 CRC2

Flag

D1 D2

TDLINT

D[7:0]

INTE

EOM

INTE

Serial Data

inserted into

Datalink

This diagram shows the relationship between XFDL inputs and outputs for the

case where interrupts and CRC are enabled for regular data transmission. The

process is started by setting the INTE bit in the Configuration/Control Register to

logic 1, thus enabling the TDLINT signal. When TDLINT is asserted, the interrupt

service routine is started, which writes the first byte (D1) of the data frame to the

Transmit Data Register. When this byte begins to be shifted out on the data link,

TDLINT is asserted. This restarts the interrupt service routine, and the next data

byte (D2) is written to the Transmit Data Register. When D2 begins to be shifted

out on the data link, TDLINT is asserted again. This cycle continues until the last

data byte (Dn) of the frame is written to the Transmit Data Register. When Dn

begins to be shifted out on the data link, TDLINT again is asserted. Since all the

data has been sent, the interrupt service routine sets the EOM bit in the

Configuration/Control Register to logic 1 (or alternatively asserts the TDLEOMI

input). The TDLINT interrupt should also be disabled at this time by setting the

INTE bit to logic 0. The XFDL will then shift out the two-byte CRC word and

closing flag, which ends the frame. Whenever new data is ready, the TDLINT

signal can be re-enabled by setting the INTE bit in the Configuration/Control

PM8313 Datasheet(PDF) 158 Page - PMC-Sierra, Inc