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LAN9250 Datasheet(PDF) 335 Page - Microchip Technology |
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LAN9250 Datasheet(HTML) 335 Page - Microchip Technology |
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335 / 421 page ![]() 2015 Microchip Technology Inc. DS00001913A-page 335 LAN9250 14.8.13 1588 CLOCK TARGET X NANOSECONDS REGISTER (1588_CLOCK_TARGET_NS_X) This read/write register combined with 1588 Clock Target x Seconds Register (1588_CLOCK_TARGET_SEC_x) form the 1588 Clock Target value. The 1588 Clock Target value is compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match. Refer to Section 14.4, "1588 Clock Events" for additional information. Note: Both this register and the 1588 Clock Target x Seconds Register (1588_CLOCK_TARGET_SEC_x) must be written for either to be affected. Note: The value read is the saved value of the 1588 Clock Target when the Clock Target Read (1588_CLOCK_TARGET_READ) bit in the 1588 Command and Control Register (1588_CMD_CTL) is set. Note: When the Clock Target Read (1588_CLOCK_TARGET_READ) bit is set, the previous value written to this register is overwritten. Normally, a read command should not be requested in between writing this register and the 1588 Clock Target x Seconds Register (1588_CLOCK_TARGET_SEC_x). Offset: Channel A: 130h Size: 32 bits Channel B: 140h Bank: Channel A: na Channel B: na Bits Description Type Default 31:30 RESERVED RO - 29:0 Clock Target NanoSeconds (CLOCK_TARGET_NS) This field contains the nanoseconds portion of the 1588 Clock Compare value. R/W 00000000h |
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