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MB91155 Datasheet(PDF) 41 Page - fujitsu semiconductor |
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MB91155 Datasheet(HTML) 41 Page - fujitsu semiconductor |
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41 / 105 page ![]() MB91F155A/MB91155/MB91154 41 • Data Direction Register (DDR) DDR2 to DDRL control the I/O direction of the I/O port by bit. DDR = 0 : Port input DDR = 1 : Port output Note : DDRI’s bit 6 is a test bit. Be sure to write “0” to the bit. “0” is the value that is read. R/W : Read/Write enabled, W : Write only, : Not in use DDR2 Initial value Access Address : 000601H 00000000B W DDR3 Initial value Access Address : 000600H 00000000B W DDR4 Initial value Access Address : 000607H 00000000B W DDR5 Initial value Access Address : 000606H 00000000B W DDR6 Initial value Access Address : 000605H 00000000B W DDR8 Initial value Access Address : 00060BH - 0000000B W DDRC Initial value Access Address : 0000FFH 00000000B R/W DDRD Initial value Access Address : 0000FEH 00000000B R/W DDRE Initial value Access Address : 0000FDH 00000000B R/W DDRF Initial value Access Address : 0000FCH - - - 00000B R/W DDRG Initial value Access Address : 000103H - - 000000B R/W DDRH Initial value Access Address : 000102H - - 000000B R/W DDRI Initial value Access Address : 000101H - 0000000B R/W DDRK Initial value Access Address : 000107H 00000000B R/W DDRL Initial value Access Address : 000106H 00000000B R/W 76 5 4 3 2 1 0 P26 P27 P25 P24 P23 P22 P21 P20 76 5 4 3 2 1 0 P36 P37 P35 P34 P33 P32 P31 P30 76 5 4 3 2 1 0 P46 P47 P45 P44 P43 P42 P41 P40 76 5 4 3 2 1 0 P56 P57 P55 P54 P53 P52 P51 P50 76 5 4 3 2 1 0 P66 P67 P65 P64 P63 P62 P61 P60 76 5 4 3 2 1 0 P86 P85 P84 P83 P82 P81 P80 76 5 4 3 2 1 0 PC6 PC7 PC5 PC4 PC3 PC2 PC1 PC0 76 5 4 3 2 1 0 PD6 PD7 PD5 PD4 PD3 PD2 PD1 PD0 76 5 4 3 2 1 0 PE6 PE7 PE5 PE4 PE3 PE2 PE1 PE0 76 5 4 3 2 1 0 PF4 PF3 PF2 PF1 PF0 76 5 4 3 2 1 0 PG5 PG4 PG3 PG2 PG1 PG0 76 5 4 3 2 1 0 PH5 PH4 PH3 PH2 PH1 PH0 76 5 4 3 2 1 0 TEST PI5 PI4 PI3 PI2 PI1 PI0 76 5 4 3 2 1 0 PK6 PK7 PK5 PK4 PK3 PK2 PK1 PK0 76 5 4 3 2 1 0 PL6 PL7 PL5 PL4 PL3 PL2 PL1 PL0 |
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