MB91155 datasheet(6/105 Pages) FUJITSU

6 / 105 page

MB91F155A/MB91155/MB91154

(Continued)

Pin No.

Pin name

Circuit

type

Function

BGRNT/P81

External bus release acceptance output

This function is enabled when external bus release acceptance output is

allowed.

Output “L” upon releasing of the external bus.

This pin is available as a port when external bus release acceptance out-

put is not allowed.

BRQ/P82

External bus release request input

This function is enabled when external bus release request input is al-

lowed.

Input “1” when the release of the external bus is desired.

This pin is available as a port when external bus release request input is

not in use.

RD/P83

External bus read strobe output

This function is enabled when external bus read strobe output is allowed.

This pin is available as a port when external bus read strobe output is not

allowed.

WR0/P84

External bus write strobe output

This function is enabled in external bus mode.

This pin is available as a port in single chip mode.

WR1/P85

External bus write strobe output

This function is enabled in external bus mode when the bus width is 16

bits.

This pin is available as a port in single chip mode or when the external bus

width is 8 bits.

CLK/P86

System clock output

The pin outputs the same clock as the external bus operating frequency.

The pin is available as a port when it is not used to output the clock.

MD2

MD1

MD0

Mode pins

To use these pins, connect them directly to either VCC or VSS.

Use these pins to set the basic MCU operating mode.

RST

External reset input

High-speed clock oscillation pins (16.5 MHz)

INT0/PC0

INT1/PC1

INT2/PC2

INT3/PC3

External interrupt request input 0-3

Since this input is used more or less continuously when the corresponding

external interrupt is allowed, output by the port needs to be stopped ex-

cept when it is performed deliberately.

Since this port is allowed to input also in standby mode, it can be used to

reset the standby state.

These pins are available as ports when external interrupt request input is

not in use.

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