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MB91155 Datasheet(PDF) 92 Page - fujitsu semiconductor |
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MB91155 Datasheet(HTML) 92 Page - fujitsu semiconductor |
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92 / 105 page ![]() MB91F155A/MB91155/MB91154 92 (7) Normal Bus Access and Read/Write Operations (VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C) *1 : If the bus is extended with either automatic wait insertion or RDY input, add the (tCYC × the number of extended cycles) time to this value. *2 : This is the value at the time of (gear cycle × 1) . When the gear cycle is set to 1/2, 1/4 or 1/8, substitute “n” in the following formula with 1/2, 1/4 or 1/8 respectively. Formula : (2 − n / 2) × tCYC − 40 Parameter Symbol Pin name Condition Value Unit Remarks Min Max CS 0 - CS3 delay time tCHCSL CLK CS0 to CS3 15 ns CS 0 - CS3 delay time tCHCSH 15 ns Address delay time tCHAV CLK A23 to A00 15 ns Data delay time tCHDV CLK D31 to D16 15 ns RD delay time tCLRL CLK RD 10 ns RD delay time tCLRH 10 ns WR0 - WR1 delay time tCLWL CLK WR0 to WR1 10 ns WR0 - WR1 delay time tCLWH 10 ns Valid address → valid data input time tAVDV A23 to A00 D31 to D16 3 / 2 × tCYC − 40 ns *1, *2 RD ↓ → valid data input time tRLDV RD D31 to D16 tCYC − 25 ns *1 Data setup → RD ↑ time tDSRH 25 ns RD ↑ → Rdata hold time tRHDX 0 ns |
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