MB91155 datasheet(60/105 Pages) FUJITSU

60 / 105 page

MB91F155A/MB91155/MB91154

External Interrupt

The external interrupt controller controls external interrupt requests input to INT pins 0 through 15.

The level of requests to be detected can be selected from “H, ” “L, ” rising edge, and falling edge.

• Block Diagram

• Register List

10. Delay Interrupt Module

The delay interrupt is a module that generates task switching interrupts. The use of this module allows the

software to generate/cancel interrupt requests to the CPU.

For the block diagram of the delay interrupt module, see section 8, “Interrupt Controller.”

• Register List

Interrupt permission register

Interrupt factor register

Request level setting register

Interrupt

request

Gate

Factor F/F

Edge detection

circuit

INT0 to INT15

EIRR0

EIRR1

ENIR0

ENIR1

ELVR0

ELVR1

(R/W)

00000000 B

000000C8H

000000C9H

000000CAH

000000CBH

000000CCH

000000CDH

000000CEH

000000CFH

bit 8

bit 15

Address

bit 0

Initial value

() : Access

R/W : Read/Write enabled

DICR

(R/W)

bit 7

Address

bit 0

Initial value

-------0 B

00000430H

() : Access

R/W : Read/Write enabled

 : Not in use

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