DM368ZCEZ datasheet(55/208 Pages) TI1

55 / 208 page

Oscillator(MXI1/MXO1)

19.2/24/27/36Mhz

SPI4

I2C

UART0

TIMER0-3/

WDT

PWM0-3

ADC

RTO

MMC/SD0

McBSP

MMC/SD1

UART1

AEMIF

SPI0-3

GPIO

AINTC

EMAC

EDMA

HPI

USBPHY

USB

CLKOUT0

CLKOUT1

DIV1

CLKOUT2

DDR

PHY

DDR2

EMIF

EXTCLK

PCLK

VPBE

VPFE

ARMSS

HDVICP

MJCP

VPSS

Voice

Codec

DIV2

DIV3

KeyScan

PRTCSS

32Khz

Oscillator

PLLC1

PLLC2

VPSS_MUXSEL

VENC_CLK_SRC

PHYCLKSRC

PRTCCLKS

KEYSCLKS

DDRCLKS

VCLK

TMS320DM368

www.ti.com

SPRS668C

– APRIL 2010 – REVISED JUNE 2011

Figure 3-2. Clocking Architecture

3.3.2

PLL Controller Module

Two PLL controllers provide clocks to different components of the chip. The PLL controller 1 (PLLC1)

provides clocks to most of the components of the chip. The PLL controller 2 (PLLC2) provides clocks to

the DDR PHY and is also capable of providing clocks to the ARM, USB, VPSS or the Voice Codec

modules instead as well.

As a module, the PLL controller provides the following:

•

Glitch-free transitions (on changing PLL settings)

•

Domain clocks alignment

•

Clock gating

Device Configurations

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DM368ZCEZ Datasheet(PDF) 55 Page - Texas Instruments

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