DM368ZCEZ datasheet(91/208 Pages) TI1

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TMS320DM368

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SPRS668C

– APRIL 2010 – REVISED JUNE 2011

•

Up to four in-flight transfer requests (TR)

•

Programmable priority level

•

Supports two dimensional transfers with independent indexes on source and destination (EDMA

Channel Controller manages the 3rd dimension)

•

Support for increment and constant addressing modes

•

Interrupt and error support

Parameter RAM: Each EDMA is specified by an eight word (32-byte) parameter table contained in

Parameter RAM (PaRAM) within the CC. The device provides 256 PaRAM entries, one for each of the 64

DMA channels and for 8 QDMA / Linked DMA entries.

DMA Channels: Can be triggered by: " External events (for example, McBSP TX Evt and RX Evt), "

Software writing a '1' to the given bit location, or channel, of the Event Set register, or, " Chaining to other

DMAs.

QDMA: The Quick DMA (QDMA) function is contained within the CC. The device implements 8 QDMA

channels. Each QDMA channel has a selectable PaRAM entry used to specify the transfer. A QDMA

transfer is submitted immediately upon writing of the "trigger" parameter (as opposed to the occurrence of

an event as with EDMA). The QDMA parameter RAM may be written by any Config bus master through

the Config Bus and by DMAs through the Config Bus bridge.

QDMA Channels: Triggered by a configuration bus write to a designated 'QDMA trigger word'. QDMAs

allow a minimum number of linear writes (optimized for GEM IDMA feature) to be issued to the CC to

force a series of transfers to take place.

6.9.1

EDMA Channel Synchronization Events

The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.

Table 6-16 lists the source of EDMA synchronization events associated with each of the programmable

EDMA channels. For the device, the association of an event to a channel is fixed; each of the EDMA

channels has one specific event associated with it. These specific events are captured in the EDMA event

registers (ER, ERH) even if the events are disabled by the EDMA event enable registers (EER, EERH).

For more detailed information on the EDMA module and how EDMA events are enabled, captured,

processed, linked, chained, and cleared, etc., see the Document Support section for the Enhanced Direct

Memory Access (EDMA) Controller Reference Guide.

Table 6-16. EDMA Channel Synchronization Events(1) (2)

EDMA

EVENT NAME

EVENT DESCRIPTION

CHANNEL

TIMER3: TEVT6

Timer 3 Interrupt (TEVT6) Event

TIMER3 TEVT7

Timer 3 Interrupt (TEVT7) Event

McBSP: XEVT or

McBSP Transmit Event or Voice Codec Transmit Event

VoiceCodec : VCREVT

McBSP :REVT or

McBSP Receive Event or Voice Codec Receive Event

VoiceCodec : VCREVT

VPSS: EVT1

VPSS Event 1

VPSS: EVT2

VPSS Event 2

VPSS: EVT3

VPSS Event 3

VPSS: EVT4

VPSS Event 4

TIMER2: TEVT4

Timer 2 interrupt (TEVT4) Event

(1)

In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or

intermediate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the Document Support

section for the Enhanced Direct Memory Access (EDMA) Controller Reference Guide.

(2)

The total number of EDMA events exceeds 64, which is the maximum value of the EDMA module. Therefore, several events are

multiplexed and you must use the register EDMA_EVTMUX in the System Control Module to select the event source for multiplexed

events. Refer to the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5) for more information on

the System Control Module register EDMA_EVTMUX.

Peripheral Information and Electrical Specifications

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