DM368ZCEZ datasheet(87/208 Pages) TI1

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TMS320DM368

www.ti.com

SPRS668C

– APRIL 2010 – REVISED JUNE 2011

6.8

General-Purpose Input/Output (GPIO)

The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.

When configured as an output, a write to an internal register can control the state driven on the output pin.

When configured as an input, the state of the input is detectable by reading the state of an internal

interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.

The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]). There

are a total of 7 GPIO banks in the device, because the device has 104 GPIOs. For additional details on

GPIO pins voltage level and the associated power supply please see Table 6-11.

Table 6-11. GPIO Pin Voltage Level and Power Supply Reference

Voltage Level

1.8 V or 3.3 V

3.3 V

1.8 V

Power Supply Name

VDD_AEMIF1_18_33

VDD_AEMIF2_18_33

VDD_ISIF18_33

VDDS33

VDD18_PRTCSS

GIO[78:68]

GIO[67]

GIO[103:93]

GIO[92:79]

GIO[110:104]

Pin Name

GIO[66:56]

GIO[55:52]

GIO[49:0]

GIO[51:50]

The GPIO peripheral supports the following:

•

Up to 104 GPIO pins, GPIO[103:0]

•

Up to 7 GPIO pins dedicated to the PRTC Subsystem. These pins are labeled as PWRCTRIO[6:0].

Only PWRCTRIO[2:0] are connected to the GPIO module, labeled as GPIO[106:104]. For the PRTCSS

module the PWRCTRIO[6:0] pins support input and output functionality but for the GPIO module the

GPIO[106:104] pins support input functionality only. For more details please refer to Section 6.7.

•

Interrupts:

– Up to 15 unique GPIO[15:0] interrupts from Bank 0.

– Up to 3 unique GPIO[106:104] interrupts from Bank 6, dedicated to the PRTC Subsystem. For

more details please refer to Section 6.7.

– Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO

signal

•

DMA events:

– Up to 15 unique GPIO DMA events from Bank 0

•

Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO

signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section

protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to

anther process during GPIO programming).

•

Separate Input/Output registers

•

Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can

be toggled by direct write to the output register(s).

•

Output register, when read, reflects output drive status. This, in addition to the input register reflecting

pin status, allows wired logic be implemented.

For more detailed information on GPIOs, see the Documentation Support section for the General-Purpose

Input/Output (GPIO) Reference Guide.

Peripheral Information and Electrical Specifications

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