DM368ZCEZ datasheet(67/208 Pages) TI1

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TMS320DM368

www.ti.com

SPRS668C

– APRIL 2010 – REVISED JUNE 2011

3.7.5

AEMIF Configuration

3.7.5.1

AEMIF Pin Configuration

The input pins AECFG[2:0] determine the AEMIF configuration immediately after reset. Pins that are not

assigned to another peripheral and not enabled as address signals become GPIOs. These may be used

as ALE and CLE signals for NAND Flash control if booting from internal ROM. If booting from NOR Flash

then the appropriate number of address output must be enabled by the AECFG[2:0] inputs at reset. The

enabled address signals are always contiguous from EM_BA[1] upwards; bits cannot be skipped. EM_A[0]

does not represent the lowest AEMIF address bit. The device has 23 address lines and 2 chip selects with

an 8-bit or 16-bit option. The device supports only 8-bit and 16-bit data widths for the AEMIF.

•

16-bit mode: EM_BA[1] represents the LS address bit (the half-word address) and EM_BA[0]

represents address bit (A[14]). The maximum number of address lines pins in 16-bit mode are 23,

which include EM_BA[1] + EM_A[0:13] +EM_BA[0] (as pin A[14] via PINMUX2 register) + EM_A[15:20]

+EM_A[21] (via PINMUX4 register)

Note: Pins EM_A[15:21] are available by programming the PinMux4 register in software after boot, but

must be pulled down externally so that valid voltage levels are provided on the full set of address pins

during boot time. EM_A[15:21] come out of reset as GPIO pins per the PinMux4 register.

•

8-bit mode: EM_BA[1:0] represent the 2 LS address bits. Additional selections are available by

programming the PinMux2 register in software after boot. The maximum number of address lines in

8-bit mode are 23, which include EM_BA[0:1] + EM_A[0:13] + A[14] (via PINMUX4 register) +

EM_A[15:20].

Note: Pins EM_A[15:20] are available by programming the PinMux4 register in software after boot, but

must be pulled down externally so that valid voltage levels are provided on the full set of address pins

during boot time. EM_A[15:20] come out of reset as GPIO pins per the PinMux4 register.

For additional details about the PinMux2 and PinMux4 registers, see the TMS320DM36x DMSoC ARM

Subsystem Reference Guide (literature number SPRUFG5).

The device's pin-mux control logic allows all of the Asynchronous EMIF address pins to be used as

GPIOs. If devices (such as NAND Flash) attached to the AEMIF require less than the 16 address pins

provided, then the unused upper-order addresses may be configured as GPIOs. These pins must be

configured at reset so that pins being driven by the AEMIF with addresses will not cause bus contention

with pins being driven by the system as general purpose inputs.

The AECFG[2:0] value does not affect the operation of the AEMIF module itself, only which of its address

bits are seen on the device pins (resulting in the natural ramifications if devices don

’t receive all address

signals or if contention with general purpose inputs occurs). As shown in Table 3-14, the number of

address bits enabled on the AEMIF is selectable from 0 to 16 at boot time, see notes above for additional

support of up-to 23 address lines.

Device Configurations

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