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DM368ZCEZ Datasheet(PDF) 89 Page - Texas Instruments |
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DM368ZCEZ Datasheet(HTML) 89 Page - Texas Instruments |
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89 / 208 page ![]() GPIx GPOx 4 3 2 1 EXT_INTx 2 1 TMS320DM368 www.ti.com SPRS668C – APRIL 2010 – REVISED JUNE 2011 Table 6-14. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see Figure 6-11) DEVICE NO. PARAMETER UNIT MIN MAX 36P(1) - 3 tw(GPOH) Pulse duration, GPOx high ns 8 36P(1) - 4 tw(GPOL) Pulse duration, GPOx low ns 8 (1) P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 3.3, Device Clocking. Figure 6-11. GPIO Port Timing 6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing Table 6-15. Timing Requirements for External Interrupts/EDMA Events(1) (see Figure 6-12) DEVICE NO. UNIT MIN MAX 1 tw(ILOW) Width of the external interrupt pulse low 2P(2) ns 2 tw(IHIGH) Width of the external interrupt pulse high 2P(2) ns (1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants the device to recognize the GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow the device enough time to access the GPIO register through the internal bus. (2) P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 3.3, Device Clocking. Figure 6-12. GPIO External Interrupt Timing 6.9 EDMA Controller The EDMA controller handles all data transfers between memories and the device slave peripherals on the device. These are summarized as follows: • Transfer to/from on-chip memories – ARM program/data RAM – HDVICP Coprocessor memory – MPEG/JPEG Coprocessor memory • Transfer to/from external storage – DDR2 / mDDR SDRAM – Asynchronous EMIF – OneNAND flash – NAND flash, NOR flash – Smart Media, SD, MMC, xD media storage Copyright © 2010–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 89 Submit Documentation Feedback Product Folder Link(s): TMS320DM368 |
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