DM368ZCEZ datasheet(57/208 Pages) TI1

57 / 208 page

TMS320DM368

www.ti.com

SPRS668C

– APRIL 2010 – REVISED JUNE 2011

3.3.3

PLLC1

There are two PLLs on the device, and they are independently controlled. PLLC1 generates the

frequencies needed for the ARM, Video Processing Sub System (VPSS), MJCP coprocessor block,

EDMA, and peripherals.

The reference clock for both PLLs is the single crystal input. Both PLLs will be of the same type . It should

be noted that the USB2.0 PHY contains a third PLL embedded within it. Table 3-2, and Figure 3-3

describe the customization of PLLC1.

•

Provides primary system clock

•

Software configurable

•

Accepts clock input or internal oscillator input

•

PLL pre-divider value is programmable

•

PLL multiplier value is programmable

•

PLL post-divider value is programmable . See the data manual for all supported configurations.

•

Only SYSCLK [9:1] are used

Table 3-2. PLLC1 Output Clocks

PLLC1SYSCLKy

Used By

PLLDIV Divider

PLLC1SYSCLK1

USB reference clock(1)

Programmable

PLLC1SYSCLK2

ARM926EJ-S, HDVICP block clock (1)

Programmable

PLLC1SYSCLK3

MJCP and HDVICP bus interface clock

Programmable

PLLC1SYSCLK4

Configuration bus clock, peripheral system interfaces,

Programmable

EDMA

PLLC1SYSCLK5

VPSS clock

Programmable

PLLC1SYSCLK6

VENC clock(1)

Programmable

PLLC1SYSCLK7

DDR 2x clock(1)

Programmable

PLLC1SYSCLK8

MMC/SD0 clock

Programmable

PLLC1SYSCLK9

CLKOUT2

Programmable

PLLC1OBSCLK

CLKOUT0

Programmable

PLLC1SYSCLKBP

USB reference clock(1)

Programmable

(1)

These clock outputs are multiplexed with other clocks.

Device Configurations

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