DM368ZCEZ datasheet(61/208 Pages) TI1

61 / 208 page

TMS320DM368

www.ti.com

SPRS668C

– APRIL 2010 – REVISED JUNE 2011

Table 3-8. 19.2-MHz Input Crystal Example(1) (2)(3)

PLL1

PLL2

ARM

DDR

MJCP

HDVICP

Voice Codec

(4)

Video Encoder

PLL Output

(5)

(2M/(N+1))

PLL Output

(2M/(N+1))

27MHz

74.25MHz

(MHz)

679.82

956/27

432

90/4

432

339.91

1/105 (16.07

1/16

kHz)

679.82

956/27

430.08

112/5

430.08

339.91

1/105

(1)

M = PLL controller multiplier. N = PLL controller divider.

(2)

All shaded frequencies derive from the PLL2 controller.

(3)

PLLC1SYSCLK4 (Configuration bus clock, peripheral system interfaces, EDMA) should be half of the PLLC1SYSCLK3 (MJCP and

HDVICP bus interface clock).

(4)

The Voice Codec divider value is the combination of the PLL controller 2 SYSCLK4 and Peripheral Clock Control Register PLLDIV2 bit

setting divider.

(5)

PLL Output is calculated by = Oscillator Input * (2M/(N+1)).

Table 3-9. 27-MHz Input Crystal Example(1) (2)(3)

PLL1

PLL2

ARM

DDR

MJCP

HDVICP

Voice Codec

USB

Video

(4)

Encoder

PLL Output

(5)

(2M/(N+1))

PLL Output

(2M/(N+1))

27 MHz

74.25MHz

(MHz)

680

680/27

432

16/1

432

340

1/105 (16.07

1/18

1/16

kHz)

680

680/27

371.25

110/8

371.25

340

1/91 (15.936

1/5

kHz)

(1)

M = PLL controller multiplier. N = PLL controller divider.

(2)

All shaded frequencies derive from the PLL2 controller.

(3)

PLLC1SYSCLK4 (Configuration bus clock, peripheral system interfaces, EDMA) should be half of the PLLC1SYSCLK3 (MJCP and

HDVICP bus interface clock).

(4)

The Voice Codec divider value is the combination of the PLL controller 2 SYSCLK4 and Peripheral Clock Control Register PLLDIV2 bit

setting divider.

(5)

PLL Output is calculated by = Oscillator Input * (2M/(N+1)).

For maximum H.264 encode performance the ARM must run at 432 MHz and the DDR at 340 MHz. Any

speed decrease to either of these will reduce encode performance. This means that if the ARM speed

must be reduced to enable another function it will impact the encode performance.

If USB is required then a 36 MHz, 24 MHz or 19.2 MHz input crystal is preferred as those can support

USB at full ARM rate.

If a video output is needed then a 36 MHz, 27 MHz or 24 MHz input crystal should be used. For HD video

output it may be preferred to use the EXTCLK input to inject an external 74.25 MHz clock and at the same

time operate the ARM at 432 MHz.

3.3.7

Peripheral Clocking Considerations

The device supports several peripherals with special clocking considerations (VPBE, USB, Key Scan,

ADC, Voice Codec, MJCP, HDVICP, AUXCLK, DDR2 EMIF). For more detail on these special

considerations, see the Peripheral Clocking Considerations section of theTMS320DM36x DMSoC ARM

Subsystem Reference Guide (literature number SPRUFG5).

3.4

Power and Sleep Controller (PSC)

In the device system, the Power and Sleep Controller (PSC) is responsible for managing transitions of

system power on/off, clock on/off, and reset. A block diagram of the PSC is shown in Figure 3-5. Many of

the operations of the PSC are transparent to software, such as power-on-reset operations. However, the

PSC provides you with an interface to control several important clock and reset operations.

The PSC includes the following features:

•

Manages chip power-on/off, clock on/off, and resets

Device Configurations

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