I960 datasheet(8/70 Pages) INTEL

8 / 70 page

ADVANCE INFORMATION

i960® Rx I/O Processor at 3.3 V

2.0

FUNCTIONAL OVERVIEW

As indicated in Figure 1, the 80960Rx combines

many features with the 80960JF to create an intelli-

gent I/O processor. Subsections following the figure

briefly describe the main features; for detailed func-

tional descriptions, refer to the

i960® RP Micropro-

cessor User’s Guide (272736).

The PCI bus is an industry standard, high perfor-

mance, low latency system bus that operates up to

132 Mbyte/s. The 80960Rx, a multi-function PCI

device, is fully compliant with the

PCI Local Bus

Specification Revision 2.1. Function 0 is the PCI-to-

PCI bridge unit; Function 1 is the address translation

unit.

The PCI-to-PCI bridge unit is the connection path

between two independent 32-bit PCI buses and

provides the ability to overcome PCI electrical load

limits. The addition of the i960 core processor brings

intelligence to the bridge.

The 80960Rx, object code compatible with the i960

core processor, is capable of sustained execution at

the rate of one instruction per clock.

The local bus, a 32-bit multiplexed burst bus, is a

high-speed interface to system memory and I/O. A

full complement of control signals simplifies the

connection of the 80960Rx to external components.

Physical

and

logical

memory

attributes

are

programmed via memory-mapped control registers

(MMRs), an extension not found on the i960 Kx, Sx

or Cx processors. Physical and logical configuration

registers enable the processor to operate with all

combinations of bus width and data object align-

ment.

Figure 1. i960

® Rx I/O Processor at 3.3 V Functional Block Diagram

PCI-to-PCI

Bridge Unit

i960® JF

Core

Processor

Secondary

PCI Arbitration

Unit

Secondary PCI Bus

Primary PCI Bus

Local Memory

2C Bus

Interface Unit

Memory

Controller

Internal

Arbitration

I2C Serial Bus

I/O APIC Bus

Interface Unit

I/O APIC Bus

Address

Translation

Unit

Two DMA

Channels

Address

Translation

Unit

One DMA

Channel

Message

Unit

Local Bus

Primary ATU

Secondary ATU

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