I960 datasheet(20/70 Pages) INTEL

20 / 70 page

i960® Rx I/O Processor at 3.3 V

ADVANCE INFORMATION

TRST#

A(L)

TEST RESET asynchronously resets the Test Access Port (TAP) controller function

of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan

feature, connect a pulldown resistor (1.5 K

Ω) between this signal and V

SS. When

TAP is not used, this signal must be connected to VSS; however, no resistor is

required. The signal has a weak internal pullup which must be overcome during reset

to ensure normal operation.

VCC

–

POWER. Connect to a 3.3 Volt VCC board plane.

VCC5

–

5 VOLT REFERENCE VOLTAGE. Input is the reference voltage for the 5 V-tolerant

I/O buffers. Connect this signal to +5 V for use with signals which exceed 3.3 V.

When all inputs are from 3.3 V components, connect this signal to 3.3 V.

VSS

–

GROUND. Connect to a VSS board plane.

N.C.

–

NO CONNECT. Do not make electrical connections to these balls.

VCCPLL3:1

PLL POWER. For external connection to a 3.3 V VCC board plane. Power to PLLs

requires external filtering.

Table 6. Interrupt Unit Signal Descriptions

NAME

TYPE

DESCRIPTION

NMI#

A(L)

NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.

NMI# is the highest priority interrupt source and is level-detect. When NMI# is

unused, it is recommended that you connect it to VCC.

S_INT[A:D]#/

XINT3:0#

A(L)

SECONDARY PCI BUS INTERRUPT

1 requests an interrupt. S_INTx# assertion

and deassertion is asynchronous to S_CLK. A device asserts S_INTx# when

requesting attention from its device driver. When S_INTx# is asserted, it remains

asserted until the device driver clears the pending request. S_INTx# Interrupts

are level sensitive.

EXTERNAL INTERRUPT. External devices use this signal to request an interrupt

service. These signals operate in dedicated mode, where each signal is assigned

a dedicated interrupt level.

The S_INT[A:D]#/XINT3:0# signals can be directed as follows:

Sec. PCI

Primary PCI

80960 Core Processor

S_INTA#

⇒

P_INTA#

XINT0#

S_INTB#

⇒

P_INTB#

XINT1#

S_INTC#

⇒

P_INTC#

XINT2#

S_INTD#

⇒

P_INTD#

XINT3#

XINT7:4#

A(L)

EXTERNAL INTERRUPT. External devices use this signal to request an interrupt

service. These signals operate in dedicated mode, where each signal is assigned

a dedicated interrupt level.

NOTE:

1. PCI signal functions are summarized in this data sheet; refer to the

PCI Local Bus Specification Revision

2.1 for a more complete definition.

Table 5. Power Requirement, Processor Control and Test Signal Descriptions (Sheet 2 of 2)

NAME

TYPE

DESCRIPTION

I960 Datasheet(PDF) 20 Page - Intel Corporation

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