I960 datasheet(4/70 Pages) INTEL

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i960® Rx I/O Processor at 3.3 V

FIGURES

Figure 1.

i960® Rx I/O Processor at 3.3 V Functional Block Diagram .......................................................... 2

Figure 2.

80960JF Core Block Diagram ........................................................................................................ 4

Figure 3.

352L HL-PBGA Package Diagram (Top and Side View) ............................................................. 21

Figure 4.

352L HL-PBGA Package Diagram (Bottom View) ....................................................................... 22

Figure 5.

Thermocouple Attachment - No Heat Sink .................................................................................. 31

Figure 6.

Thermocouple Attachment - With Heat Sink ................................................................................ 31

Figure 7.

VCC5 Current-Limiting Resistor ................................................................................................... 34

Figure 8.

AC Test Load ............................................................................................................................... 44

Figure 9.

S_CLK, TCLK Waveform ............................................................................................................. 44

Figure 10. TOV Output Delay Waveform ....................................................................................................... 45

Figure 11. TOF Output Float Waveform .........................................................................................................45

Figure 12. TIS and TIH Input Setup and Hold Waveform ............................................................................... 46

Figure 13. TLXL and TLXA Relative Timings Waveform ................................................................................. 46

Figure 14. DT/R# and DEN# Timings Waveform .......................................................................................... 47

Figure 15. I2C Interface Signal Timings ........................................................................................................ 47

Figure 16. Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960 Local Bus ... 48

Figure 17. Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960 Local Bus . 49

Figure 18. FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States .......................................... 50

Figure 19. FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States ........................................... 51

Figure 20. EDO DRAM, Read Cycle ............................................................................................................. 52

Figure 21. EDO DRAM, Write Cycle ............................................................................................................. 52

Figure 22. BEDO DRAM, Read Cycle ........................................................................................................... 53

Figure 23. BEDO DRAM, Write Cycle ........................................................................................................... 53

Figure 24. 32-Bit Bus, SRAM Read Accesses with 0 Wait States ................................................................ 54

Figure 25. 32-Bit Bus, SRAM Write Accesses with 0 Wait States ................................................................ 54

Figure 26. Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus .............. 55

Figure 27. Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus ...................... 56

Figure 28. Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus ................................ 57

Figure 29. Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus ........................ 58

Figure 30. Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on Read,

16-Bit 80960 Local Bus ................................................................................................................ 59

Figure 31. Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte From

Quad Word Boundary, 32-Bit 80960 Local Bus ........................................................................... 60

Figure 32. HOLD/HOLDA Waveform For Bus Arbitration ............................................................................. 61

Figure 33. 80960 Core Cold Reset Waveform .............................................................................................. 62

Figure 34. 80960 Local Bus Warm Reset Waveform .................................................................................... 63

I960 Datasheet(PDF) 4 Page - Intel Corporation

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