I960 datasheet(5/70 Pages) INTEL

5 / 70 page

TABLES

Table 1.

Related Documentation ................................................................................................................. 1

Table 2.

80960Rx Instruction Set ................................................................................................................ 7

Table 3.

Signal Type Definition .................................................................................................................... 8

Table 4.

Signal Descriptions ........................................................................................................................ 9

Table 5.

Power Requirement, Processor Control and Test Signal Descriptions ....................................... 13

Table 6.

Interrupt Unit Signal Descriptions .................................................................................... ............ 14

Table 7.

PCI Signal Descriptions ............................................................................................... ................ 15

Table 8.

Memory Controller Signal Descriptions ....................................................................................... 18

Table 9.

DMA, APIC, I2C Units Signal Descriptions .................................................................................. 19

Table 10.

Clock Signal ................................................................................................................................. 20

Table 11.

ICE Signal Descriptions ............................................................................................................... 20

Table 12.

352-Lead HL-PBGA Package — Signal Name Order (Sheet 1 of 4) ........................................... 23

Table 13.

352-Lead HL-PBGA Pinout — Ballpad Number Order (Sheet 1 of 4) ......................................... 27

Table 14.

352-Lead HL-PBGA Package Thermal Characteristics ............................................................... 32

Table 15.

Heatsink Information .................................................................................................................... 33

Table 16.

Operating Conditions ................................................................................................................... 34

Table 17.

VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V) ....................................... 34

Table 18.

DC Characteristics ....................................................................................................................... 35

Table 19.

ICC Characteristics ....................................................................................................................... 36

Table 20.

Input Clock Timings ..................................................................................................................... 37

Table 21.

Synchronous Output Timings ...................................................................................................... 37

Table 22.

Synchronous Input Timings ......................................................................................................... 38

Table 23.

Relative Output Timings .............................................................................................................. 39

Table 24.

Fast Page Mode Non-interleaved DRAM Output Timings ........................................................... 39

Table 25.

Fast Page Mode Interleaved DRAM Output Timings ................................................................... 40

Table 26.

EDO DRAM Output Timings ........................................................................................................ 40

Table 27.

BEDO DRAM Output Timings ...................................................................................................... 41

Table 28.

SRAM/ROM Output Timings ........................................................................................................ 41

Table 29.

Boundary Scan Test Signal Timings ............................................................................................ 42

Table 30.

APIC Bus Interface Signal Timings .............................................................................................. 42

Table 31.

I2C Interface Signal Timings ........................................................................................................ 43

Table 32.

Processor Device ID Register - PDIDR ...................................................................................... 64

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