I960 datasheet(43/70 Pages) INTEL

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i960

® Rx I/O Processor at 3.3 V

ADVANCE INFORMATION

4.4

Targeted AC Specifications

Table 20. Input Clock Timings

Symbol

Parameter

Min

Max

Units

Notes

S_CLK Frequency

33.33

MHz

S_CLK Period

62.5

(1)

TCS

S_CLK Period Stability

±250

Adjacent Clocks (2,3)

TCH

S_CLK High Time

Measured at 1.5 V (2,3)

TCL

S_CLK Low Time

Measured at 1.5 V (2,3)

TCR

S_CLK Rise Time

V/ns

0.4 V to 2.4 V (2,3)

TCF

S_CLK Fall Time

V/ns

2.4 V to 0.4 V (2,3)

NOTES:

1. See Figure 9.

2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum

should not have any power peaking between 500 KHz and 1/3 of the S_CLK frequency.

3. Not tested.

Table 21. Synchronous Output Timings

Symbol

Parameter

Min

Max

Units

Notes

TOV1

Output Valid Delay - All Local Bus Signals Except

ALE Inactive and DT/R#

15.5

(1,2,5)

TOV2

Output Valid Delay, DT/R#

0.5 TC +3 0.5 TC +15

(2,5)

TOV3

Output Valid Delay - PCI Signals Except P_REQ#,

S_GNT0#/S_REQ#, and S_GNT5:1#

211

(2,5)

TOV4

Output Valid Delay P_REQ#, S_GNT0#/S_REQ#,

and S_GNT5:1#

212

(2,5)

TOV5

Output Valid Delay - DP3:0

(2,5)

TOF

Output Float Delay

(3,4,5)

NOTES:

1. Inactive ALE refers to the falling edge of ALE. For inactive ALE timings, see Table 23, Relative Output Timings (pg. 39).

2. See Figure 10, TOV Output Delay Waveform (pg. 45).

3. A float condition occurs when the output current becomes less than ILO. Float delay is not tested, but is designed to be no

longer than the valid delay.

4. See Figure 11, TOF Output Float Waveform (pg. 45).

5. Outputs precharged to VCC5 maximium.

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