I960 datasheet(16/70 Pages) INTEL

16 / 70 page

i960® Rx I/O Processor at 3.3 V

ADVANCE INFORMATION

BE3:0#

R(1)

H(Z)

P(1)

BYTE ENABLES select which of up to four data bytes on the bus participate

in the current bus access. Byte enable encoding depends on the bus width

of the memory region accessed:

32-bit bus:

BE3# enables data on AD31:24

BE2# enables data on AD23:16

BE1# enables data on AD15:8

BE0# enables data on AD7:0

16-bit bus:

BE3# becomes Byte High Enable (enables data on AD15:8)

BE2# is not used (state is high)

BE1# becomes Address Bit 1 (A1)

(increments with the assertion of LRDY# or RDYRCV#)

BE0# becomes Byte Low Enable (enables data on AD7:0)

8-bit bus:

BE3# is not used (state is high)

BE2# is not used (state is high)

BE1# becomes Address Bit 1 (A1)

(increments with the assertion of LRDY# or RDYRCV#)

BE0# becomes Address Bit 0 (A0)

(increments with the assertion of LRDY# or RDYRCV#)

The processor asserts byte enables, byte high enable and byte low enable

during Ta. Since unaligned bus requests are split into separate bus transac-

tions, these signals do not toggle during a burst (32-bit bus only) from the

i960 core processor; they do toggle for DMA and ATU cycles. They remain

active through the last Td cycle.

DEN#

H(Z)

P(1)

DATA ENABLE indicates data transfer cycles during a bus access. DEN# is

asserted at the start of the first data cycle in a bus access and deasserted at

the end of the last data cycle. DEN# is used with DT/R# to provide control for

data transceivers connected to the data bus. DEN# has a weak internal

pullup which is active during reset to ensure normal operation when the

signal is not connected.

0 = Data Cycle

1 = Not a Data Cycle

Table 4. Signal Descriptions (Sheet 2 of 5)

NAME

TYPE

DESCRIPTION

I960 Datasheet(PDF) 16 Page - Intel Corporation

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