I960 datasheet(9/70 Pages) INTEL

9 / 70 page

i960

® Rx I/O Processor at 3.3 V

ADVANCE INFORMATION

2.1

Key Functional Units

2.1.1

PCI-to-PCI Bridge Unit

The PCI-to-PCI bridge unit (referred to as “bridge”)

connects two independent PCI buses. It is fully

compliant with the

PCI-to-PCI Bridge Architecture

Specification Revision 1.0 published by the PCI

Special Interest Group. It allows certain bus transac-

tions on one PCI bus to be forwarded to the other

PCI bus. Dedicated data queues support high perfor-

mance bandwidth on the PCI buses. The i960® Rx

I/O Processor at 3.3 V supports PCI 64-bit Dual

Address Cycle (DAC) addressing.

The bridge has dedicated PCI configuration space

that is accessible through the primary PCI bus.

2.1.2

Private PCI Device Support

A key design feature is that the 80960Rx explicitly

supports private PCI devices on the secondary PCI

bus without being detected by PCI configuration soft-

ware. The bridge and Address Translation Unit work

together to hide private devices from PCI configura-

tion cycles and allow these devices to use a private

PCI address space. The Address Translation Unit

uses normal PCI configuration cycles to configure

these devices.

2.1.3

DMA Controller

The DMA Controller supports low-latency, high-

throughput data transfers between PCI bus agents

and 80960 local memory. Three separate DMA

channels accommodate data transfers: two for

primary PCI bus, one for the secondary PCI bus.

The

DMA

Controller

supports

chaining

and

unaligned data transfers. It is programmable only

through the i960 core processor.

2.1.4

Address Translation Unit

The Address Translation Unit (ATU) allows PCI

transactions direct access to the 80960Rx local

memory. The 80960Rx has direct access to both PCI

buses. The ATU supports transactions between PCI

address space and 80960Rx address space.

Address translation is controlled through program-

mable registers accessible from both the PCI inter-

face and the 80960 core. Dual access to registers

allows flexibility in mapping the two address spaces.

2.1.5

Messaging Unit

The Messaging Unit (MU) provides data transfer

between the PCI system and the 80960Rx. It uses

interrupts to notify each system when new data

arrives. The MU has four messaging mechanisms.

Each allows a host processor or external PCI device

and the 80960Rx to communicate through message

passing and interrupt generation. The four mecha-

nisms are Message Registers, Doorbell Registers,

Circular Queues, and Index Registers.

2.1.6

Memory Controller

The Memory Controller allows direct control of

external memory systems, including DRAM, SRAM,

ROM and Flash Memory. It provides a direct connect

interface to memory that typically does not require

external logic. It features programmable chip selects,

a wait state generator and byte parity. External

memory can be configured as PCI addressable

memory or private processor memory.

2.1.7

I2C Bus Interface Unit

The I2C (Inter-Integrated Circuit) Bus Interface Unit

allows the 80960 core to serve as a master and

slave device residing on the I2C bus. The I2C bus is

a serial bus developed by Philips Semiconductor

consisting of a two pin interface. The bus allows the

80960Rx to interface to other I2C peripherals and

microcontrollers for system management functions.

It requires a minimum of hardware for an economical

system to relay status and reliability information on

the I/O subsystem to an external device. For more

information, see

I2C Peripherals for Microcontrollers

(Philips Semiconductor)

2.1.8

I/O APIC Bus Interface Unit

The I/O APIC Bus Interface Unit provides an inter-

face to the three-wire Advanced Programmable

Interrupt Controller (APIC) bus that allows I/O APIC

emulation in software. Interrupt messages can be

sent on the bus and EOI messages can be received.

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