I960 datasheet(24/70 Pages) INTEL

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i960® Rx I/O Processor at 3.3 V

ADVANCE INFORMATION

Table 8. Memory Controller Signal Descriptions (Sheet 1 of 2)

NAME

TYPE

DESCRIPTION

CAS7:0#

R(1)

H(Q)

P(Q)

COLUMN ADDRESS STROBE signals are used for DRAM accesses and are

asserted when the MA11:0 signals contain a valid column address. CAS7:0#

signals are asserted during refresh.

Non-Interleaved Operation:

CAS0#,CAS4# = BE0#

lane access

CAS1#,CAS5# = BE1#

lane access

CAS2#,CAS6# = BE2#

lane access

CAS3#,CAS7# = BE3#

lane access

Interleaved Operation:

CAS0# = BE0#

Even leaf lane access

CAS1# = BE1#

Even leaf lane access

CAS2# = BE2#

Even leaf lane access

CAS3# = BE3#

Even leaf lane access

CAS4# = BE0#

Odd leaf lane access

CAS5# = BE1#

Odd leaf lane access

CAS6# = BE2#

Odd leaf lane access

CAS7# = BE3#

Odd leaf lane access

CE1:0#

R(1)

H(Q)

P(Q)

CHIP ENABLE signals indicate an access to one of the two SRAM/ FLASH/

ROM memory banks. CE0# and CE1# are never asserted at the same time.

These signals are valid during the entire memory operation. CE0# is asserted

for accesses to memory bank 0. CE1# is asserted for accesses to memory

bank 1.

DALE1:0

R(0)

H(Q)

P(Q)

DRAM ADDRESS LATCH ENABLE signals support external address demul-

tiplexing of the MA11:0 address lines for interleaved DRAM systems. Use

these to directly interface to ‘373’ type latches. These signals are only valid for

accesses to interleaved memory systems. DALE0 is asserted during a valid

even leaf address. DALE1 is asserted during a valid odd leaf address.

DP3:0

I/O

R(X)

H(Q)

P(Q)

DATA PARITY carries the parity information for DRAM accesses. Each parity

bit corresponds to a group of 8 data bus signals as follows:

DP0 — AD7:0

DP2 — AD23:16

DP1 — AD15:8

DP3 — AD31:24

The memory controller generates parity information for local bus writes during

data cycles. During read data cycles, the memory controller checks parity and

provides notification of parity errors on the clock following the data cycle.

Parity checking and polarity are user-programmable. Parity generation and

checking are valid only for data lines that have their associated enable bits

asserted.

DWE1:0#

R(1)

H(Q)

P(Q)

DRAM WRITE ENABLE signals distinguish between read and write accesses

to DRAM. DWE1:0# lines are asserted for writes and deasserted for reads.

CAS7:0# determine valid bytes lanes during the access. These two outputs

are functionally equivalent for all DRAM accesses; these provide increased

drive capability for heavily loaded systems.

LEAF1:0#

R(1)

H(Q)

P(Q)

LEAF ENABLE signals control the data output enables of the memory system

during an interleaved DRAM read access. Use these to directly interface to

either DRAM or transceiver output enable signals. LEAF0# is asserted during

an even leaf access. LEAF1# is asserted during an odd leaf access.

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