I960 datasheet(26/70 Pages) INTEL

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i960® Rx I/O Processor at 3.3 V

ADVANCE INFORMATION

SCL

I/O

R(Z)

H(Q)

P(Q)

2C CLOCK provides synchronous I2C bus operation.

SDA

I/O

R(Z)

H(Q)

P(Q)

2C DATA used for data transfer and arbitration on the I2C bus.

WAIT#

R(1)

H(Q)

P(Q)

WAIT is an output that allows the DMA controller to insert wait states during

DMA accesses to an external memory system.

Table 10. Clock Signal

NAME

TYPE

DESCRIPTION

S_CLK

SYNCHRONOUS PCI BUS CLOCK Provides the processor’s fundamental time

base. All input/output timings are relative to S_CLK.

Table 11. ICE Signal Descriptions

NAME

TYPE

DESCRIPTION

ICEADS#

ICE ADDRESS/DATA STATUS indicates a valid address and the start of a new

bus access. ICEADS# is active for accesses to external microcode.

ICEBRK#

ICE BREAK forces the processor to transition from emulation to interrogation

mode.

ICEBUS7:0

I/O

ICE BUS is a bidirectional 8-bit bus linking the processor and the emulator.

Used in various modes.

ICECLK

ICE CLOCK output signal to which all ICE bus signals are synchronized.

ICELOCK#

ICE LOCK is sampled during 80960 core reset to protect ICE configuration.

ICEMSG#

ICE MESSAGE signal used to acknowledge data from the processor to the

emulator. Used only during interrogation mode.

ICESEL#

ICESEL enables or disables the ICE unit.

ICEVLD#

ICE VALID indicates the processor is driving the ICEBUS with valid data.

MSGFRM#

ICE MESSAGE FRAME indicates that trace messages are being issued to the

ICEBUS. Used in emulation mode only.

Table 9. DMA, APIC, I2C Units Signal Descriptions (Sheet 2 of 2)

NAME

TYPE

DESCRIPTION

I960 Datasheet(PDF) 26 Page - Intel Corporation

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