I960 datasheet(18/70 Pages) INTEL

18 / 70 page

i960® Rx I/O Processor at 3.3 V

ADVANCE INFORMATION

HOLD

S(L)

HOLD is a request from an external bus master to acquire the bus. When the

processor receives HOLD and grants bus control to another master, it

asserts HOLDA, floats the address/data and control lines and enters the Th

state. When HOLD is deasserted, the processor deasserts HOLDA and

enters either the Ti or Ta state, resuming control of the address/data and

control lines. See Figure 32, HOLD/HOLDA Waveform For Bus Arbitration

(pg. 61).

0 = No Hold Request

1 = Hold Requested

HOLDA

R(0)

H(1)

P(Q)

HOLD ACKNOWLEDGE indicates to an external bus master that the

processor has relinquished bus control. The processor can grant HOLD

requests and enter the Th state and while halted as well as during regular

operation. See Figure 32, HOLD/HOLDA Waveform For Bus Arbitration (pg.

61).

0 = No Hold Acknowledged

1 = Hold Acknowledged

RDYRCV#

S(L)

READY/RECOVER is only used in systems that use an external memory

controller (and do not use the 80960Rx’s memory controller unit). This signal

indicates that data on AD lines can be sampled or removed. When

RDYRCV# is not asserted during a Td cycle, the Td cycle extends to the next

cycle by inserting a wait state (Tw).

0 = Sample Data

1 = Do Not Sample Data

RDYRCV# has an alternate function during the recovery (Tr) state. The

processor continues to insert recovery states until it samples the signal

HIGH. This gives slow external devices more time to float their buffers

before the processor drives addresses.

0 = Insert Wait States

1 = Recovery Complete

When using the internal memory controller, connect this signal to VCC

through a 2.7 K

Ω resistor.

W/R#

R(0)

H(Z)

P(Q)

WRITE/READ specifies during a Ta cycle whether the operation is a write or

read. It is latched on-chip and remains valid during Td cycles.

0 = Read

1 = Write

WIDTH/

HLTD0

I/O

R(H)

H(Z)

P(Q)

WIDTH denotes the physical memory attributes for a bus transaction in

conjunction with WIDTH/HLTD1/RETRY:

WIDTH/HLTD1/RETRY

WIDTH/HLTD0

8 Bits Wide

16 Bits Wide

32 Bits Wide

Undefined

WIDTH/HLTD0 For proper operation, do not connect this signal to ground.

This signal has a weak internal pullup which is active during reset to ensure

normal operation.

HLTD0 signal name has no function in the 80960Rx; the signal name is

included for 80960JF naming convention compatibility.

Table 4. Signal Descriptions (Sheet 4 of 5)

NAME

TYPE

DESCRIPTION

I960 Datasheet(PDF) 18 Page - Intel Corporation

I960 Datasheet(HTML) 18 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Download

Link URL