I960 datasheet(19/70 Pages) INTEL

19 / 70 page

i960

® Rx I/O Processor at 3.3 V

ADVANCE INFORMATION

WIDTH/

HLTD1/

RETRY

I/O

R(H)

H(Z)

P(Q)

WIDTH denotes the physical memory attributes for a bus transaction in

conjunction with the WIDTH/HLTD0 signal. Refer to description above.

RETRY is sampled at Primary PCI bus reset to determine when the Primary

PCI interface is disabled. When high, the Primary PCI interface disables PCI

configuration cycles by signaling a RETRY until the Extended Bridge Control

PCI interface allows configuration cycles to occur. WIDTH/HLTD1/RETRY

has a weak internal pullup which is active during reset to ensure normal

operation when the signal is not connected.

HLTD1 signal name has no function in the 80960Rx; the signal name is

included for 80960JF naming convention compatibility.

Table 5. Power Requirement, Processor Control and Test Signal Descriptions (Sheet 1 of 2)

NAME

TYPE

DESCRIPTION

FAIL#

R(0)

H(Q)

FAIL indicates a failure of the processor’s built-in self-test performed during initial-

ization. FAIL# is asserted immediately upon reset and toggles during self-test to

indicate the status of individual tests:

• When self-test passes, the processor deasserts FAIL# and commences operation

from user code.

• When self-test fails, the processor asserts FAIL# and then stops executing. Self-

test failing does not cause the bridge to stop execution.

0 = Self Test Failed

1 = Self Test Passed

L_RST#

LOCAL BUS RESET notifies external devices that the local bus has reset.

STEST

S(L)

SELF TEST enables or disables the processor’s internal self-test feature at initial-

ization. STEST is examined at the end of P_RST#. When STEST is asserted, the

processor performs its internal self-test and the external bus confidence test. When

STEST is deasserted, the processor performs only the external bus confidence test.

0 = Self Test Disabled

1 = Self Test Enabled

TCK

TEST CLOCK is a CPU input that provides the clocking function for IEEE 1149.1

Boundary Scan Testing (JTAG). State information and data are clocked into the

processor on the rising edge; data is clocked out of the processor on the falling edge.

TDI

S(L)

TEST DATA INPUT is the serial input signal for JTAG. TDI is sampled on the rising

edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.

This signal has a weak internal pullup which is active during reset to ensure normal

operation when the signal is not connected.

TDO

R(Q)

H(Q)

P(Q)

TEST DATA OUTPUT is the serial output signal for JTAG. TDO is driven on the

falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access

Port. At other times, TDO floats.

TMS

S(L)

TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of

the test logic for IEEE 1149.1 Boundary Scan testing. This signal has a weak internal

pullup which is active during reset to ensure normal operation when the signal is not

connected.

Table 4. Signal Descriptions (Sheet 5 of 5)

NAME

TYPE

DESCRIPTION

I960 Datasheet(PDF) 19 Page - Intel Corporation

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