I960 datasheet(45/70 Pages) INTEL

45 / 70 page

i960

® Rx I/O Processor at 3.3 V

ADVANCE INFORMATION

4.4.1

Relative Output Timings

4.4.2

Memory Controller Relative Output Timings

Table 23. Relative Output Timings

Symbol

Parameter

Min

Max

Units

Notes

TLXL

ALE Width

0.5TC-3

(1,2,4)

TLXA

Address Hold from ALE Inactive

0.5TC-3

Equal Loading (1,2,4)

TDXD

DT/R# Valid to DEN# Active

0.5TC-3

Equal Loading (1,3,4)

NOTES:

1. Guaranteed by design. May not be 100% tested.

2. See Figure 13.

3. See Figure 14.

4. Outputs precharged to VCC5 maximium.

Table 24. Fast Page Mode Non-interleaved DRAM Output Timings

Symbol

Description

Min

Max

Units

Notes

TOV6

RAS3:0# Rising and Falling edge Output Valid

Delay

TOV7

CAS7:0# Rising Edge Output Valid Delay

TOV8

CAS7:0# Falling Edge Output Valid Delay

0.5Tc+2

0.5Tc+8

1,2

TOV9

MA11:0 Output Valid Delay-Row Address

0.5Tc+2

0.5Tc+10

1,2

TOV10

MA11:0 Output Valid Delay-Column Address

TOV11

DWE1:0# Rising and Falling edge Output Valid

Delay

211

NOTES:

1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK

period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset.

2. Output switching between VCC3 maximium and VSS.

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