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I960 Datasheet(PDF) 46 Page - Intel Corporation |
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I960 Datasheet(HTML) 46 Page - Intel Corporation |
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46 / 70 page  i960® Rx I/O Processor at 3.3 V 40 ADVANCE INFORMATION Table 25. Fast Page Mode Interleaved DRAM Output Timings Symbol Description Min Max Units Notes TOV12 RAS3:0# Rising and Falling edge Output Valid Delay 2 9 ns 2 TOV13 CAS7:0# Rising Edge Output Valid Delay 2 8 ns 2 TOV14 CAS7:0# Falling Edge Output Valid Delay 0.5Tc+2 0.5Tc+8 ns 1,2 TOV15 MA11:0 Output Valid Delay-Row Address 0.5Tc+2 0.5Tc+10 ns 1,2 TOV16 MA11:0 Output Valid Delay-Column Address 2 10 ns 2 TOV17 DWE1:0# Rising and Falling Edge Output Valid Delay 2 11 ns 2 TOV18 DALE1:0 Initial Falling Edge Output Valid Delay 2 10 ns 2 TOV19 DALE1:0 Burst Falling Edge Output Valid Delay 0.5Tc+2 0.5Tc+10 ns 1,2 TOV20 DALE1:0 Rising Edge Output Valid Delay 2 10 ns 2 TOV21 LEAF1:0# Rising and Falling Edge Output Valid Delay 210 ns 2 NOTE: 1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset. 2. Output switching between VCC3 maximium and VSS. Table 26. EDO DRAM Output Timings Symbol Description Min Max Units Notes TOV22 RAS3:0# Rising and Falling Edge Output Valid Delay 2 9 ns 2 TOV23 CAS7:0# Rising Edge Output Valid Delay - Read Cycles 0.5Tc+2 0.5Tc+8 ns 1,2 TOV24 CAS7:0# Falling Edge Output Valid Delay - Read Cycles 28 ns 2 TOV25 CAS7:0# Rising Edge Output Valid Delay - Write Cycles 28 ns 2 TOV26 CAS7:0# Falling Edge Output Valid Delay - Write Cycles 0.5Tc+2 0.5Tc+8 ns 1,2 TOV27 MA11:0 Output Valid Delay - Row Address 0.5Tc+2 0.5Tc+10 ns 1,2 TOV28 MA11:0 Output Valid Delay - Column Address Read Cycles 0.5Tc+2 0.5Tc+10 ns 1,2 TOV29 MA11:0 Output Valid Delay - Column Address Write Cycles 2 10 ns 2 TOV30 DWE1:0# Rising and Falling Edge Output Valid Delay 2 11 ns 2 NOTES: 1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset. 2. Output switching between VCC3 maximium and VSS. |
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