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I960 Datasheet(PDF) 44 Page - Intel Corporation

Part # I960
Description  i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS
PDF  70 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

I960 Datasheet(HTML) 44 Page - Intel Corporation

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i960® Rx I/O Processor at 3.3 V
38
ADVANCE INFORMATION
Table 22. Synchronous Input Timings
Sym
Parameter
Min
Max
Units
Notes
TIS1
Input Setup to S_CLK — NMI#, XINT7:4#, S_INT[A:D]#/XINT3:0#,
DP3:0#
6
ns
(1,2)
TIS1A
Input Setup to S_CLK — for all accesses except Expansion ROM
Accesses — AD31:0 only
6
ns
(1,2)
TIS1B
Input Setup to S_CLK during Expansion ROM Accesses —
AD31:0 only
8
ns
(1,2)
TIH1
Input Hold from S_CLK — AD31:0, NMI#, XINT7:4#,
S_INT[A:D]#/XINT3:0#, DP3:0#
2
ns
(1,2,4)
TIS2
Input Setup to S_CLK — RDYRCV# and HOLD
10
ns
(2)
TIH2
Input Hold from S_CLK — RDYRCV# and HOLD
2
ns
(2)
TIS3
Input Setup to S_CLK — LOCK#/ONCE#, STEST
7
ns
(1,2)
TIH3
Input Hold from S_CLK — LOCK#/ONCE#, STEST
3
ns
(1,2)
TIS4
Input Setup to S_CLK — DREQ#
12
ns
(2)
TIH4
Input Hold from S_CLK — DREQ#
7
ns
(2)
TIS5
Input Setup to S_CLK — PCI Signals Except P_GNT#,
S_REQ0#/S_GNT#, and S_REQ5:1#
7ns
(2)
TIH5
Input Hold from S_CLK — PCI Signals
0
ns
(2,4)
TIS6
Input Setup to S_CLK — P_RST#
6
ns
(2,3)
TIH6
Input Hold to S_CLK — P_RST#
2
ns
(2,3)
TIS7
Input Setup to S_CLK — P_GNT#
10
ns
(2)
TIS8
Input Setup to S_CLK — S_REQ0#/S_GNT# and S_REQ5:1#
12
ns
(2)
TIS9
Input Setup to P_RST# —
WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE#
7
ns
(1,2,4)
TIH9
Input Hold from P_RST# —
WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE#
3
ns
(1,2,4)
NOTES:
1. Setup and hold times must be met for proper processor operation. NMI#, XINT7:4#, and S_INT[A:D]#/XINT3:0# may be
synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge.
For asynchronous operation, NMI#, XINT7:4#, and S_INT[A:D]#/XINT3:0# must be asserted for a minimum of two S_CLK
periods to guarantee recognition.
2. See Figure 12, TIS and TIH Input Setup and Hold Waveform (pg. 46).
3. P_RST# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge.
4. Guaranteed by design. May not be 100% tested.



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