I960 datasheet(49/70 Pages) INTEL

49 / 70 page

i960

® Rx I/O Processor at 3.3 V

ADVANCE INFORMATION

4.4.5

I2C Interface Signal Timings

TAPIS1

Input Setup to PICCLK — PICD1:0

TAPIH1

Input Hold from PICCLK — PICD1:0

2.5

TAPOF

Output Float Delay from PICCLK — PICD1:0

(1)

TAPOVI

Output Valid Delay from PICCLK — PICD1:0 (High to Low)

Table 31. I2C Interface Signal Timings

Symbol

Parameter

Std. Mode

Fast Mode

Units

Notes

Min

Max

Min

Max

FSCL

SCL Clock Frequency

100

400

KHz

TBUF

Bus Free Time Between STOP and START

Condition

4.7

1.3

µs(1)

THDSTA

Hold Time (repeated) START Condition

0.6

µs

(1,3)

TLOW

SCL Clock Low Time

4.7

1.3

µs

(1,2)

THIGH

SCL Clock High Time

0.6

µs

(1,2)

TSUSTA

Setup Time for a Repeated START Condition

4.7

0.6

µs(1)

THDDAT

Data Hold Time

0.9

µs(1)

TSUDAT

Data Setup Time

250

100

(1)

SCL and SDA Rise Time

1000

20+0.1Cb

300

(1,4)

SCL and SDA Fall Time

300

20+0.1Cb

300

(1,4)

TSUSTO

Setup Time for STOP Condition

0.6

µs(1)

NOTES:

1. See Figure 15.

2. Not tested.

3. After this period, the first clock pulse is generated.

4. Cb = the total capacitance of one bus line, in pF.

Table 30. APIC Bus Interface Signal Timings (Sheet 2 of 2)

Symbol

Parameter

Min

Max

Units

Notes

NOTES:

1. Not tested.

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