I960 datasheet(23/70 Pages) INTEL

23 / 70 page

i960

® Rx I/O Processor at 3.3 V

ADVANCE INFORMATION

S_LOCK#

I/O

R(Z)

SECONDARY PCI BUS LOCK indicates the need to perform an atomic

operation on the secondary PCI bus.

S_PAR

I/O

R(0)

SECONDARY PCI BUS PARITY. This signal ensures even parity across

S_AD31:0 and S_C/BE3:0. All PCI devices must provide a parity signal.

S_PERR#

I/O

R(Z)

SECONDARY PCI BUS PARITY ERROR is used for reporting data parity

errors during all PCI transactions except a special cycle.

S_REQ0#/

S_GNT#

SECONDARY PCI BUS REQUEST0 is a request signal from device 0 on

the secondary PCI bus when the internal Secondary PCI Bus Arbiter is

enabled.

SECONDARY PCI BUS GRANT is the grant signal for the 80960Rx when

the arbiter is disabled.

S_RST#

R(Q)

SECONDARY PCI BUS RESET is an output based on P_RST#. It brings

PCI-specific registers, sequencers, and signals to a consistent state. When

P_RST# is asserted, it causes S_RST# to assert, and:

• PCI output signals are driven to a known consistent state.

• PCI bus interface output signals are three-stated.

• open drain signals such as S_SERR# are floated.

S_RST# may be asynchronous to S_CLK when asserted or deasserted.

S_SERR#

I/O

R(Z)

SECONDARY PCI BUS SYSTEM ERROR reports address and data parity

errors on the special cycle command, or any other system error where the

result would be catastrophic.

S_STOP#

I/O

R(Z)

SECONDARY PCI BUS STOP indicates that the current target is

requesting the master to stop the current transaction on the secondary PCI

bus.

S_TRDY#

I/O

R(Z)

SECONDARY PCI BUS TARGET READY indicates the target agent's

(selected device's) ability to complete the current data phase of the trans-

action.

S_REQ4:1#

S(L)

SECONDARY PCI BUS REQUEST 4:1 are request signals from devices

1-4 on the secondary PCI bus.

S_REQ5#/

S_ARB_EN

S(L)

SECONDARY PCI BUS REQUEST 5 is the request signal from device 5 on

the secondary PCI bus.

SECONDARY PCI BUS ARBITER ENABLE defines the power-up status

of the internal secondary arbitration unit. A valid high at the deassertion of

P_RST# enables the internal secondary arbiter. A valid low at the

deassertion of P_RST# disables the internal secondary arbiter.

Table 7. PCI Signal Descriptions (Sheet 3 of 3)

NAME

TYPE

DESCRIPTION1

NOTE:

1. PCI signal functions are summarized in this data sheet; refer to the

PCI Local Bus Specification Revision

2.1 for a more complete definition.

I960 Datasheet(PDF) 23 Page - Intel Corporation

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