I960 datasheet(17/70 Pages) INTEL

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i960

® Rx I/O Processor at 3.3 V

ADVANCE INFORMATION

D/C#/

RST_MODE#

I/O

R(H)

H(Z)

P(Q)

DATA/CODE/RESET_MODE indicates that a bus access is a data access

or an instruction access. D/C# has the same timing as W/R#.

0 = Instruction Access

1 = Data Access

The RST_MODE# signal is sampled at Primary PCI bus reset to determine

whether the 80960 core is to be held in reset. When RST_MODE# is high,

the 80960Rx begins initialization immediately following the deassertion of

P_RST. When RST_MODE is low, the 80960 core remains in reset until the

80960 core reset bit is cleared in the extended bridge control register. This

signal has a weak internal pullup that is active during reset to ensure normal

operation when the signal is left unconnected.

0 = RST_MODE enabled

1 = RST_MODE not enabled

While the 80960 core is in reset, all peripherals may be accessed from the

primary or secondary PCI buses depending on the status of the

WIDTH/HLTD1/RETRY/ signal.

DT/R#

R(0)

H(Z)

P(Q)

DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and

from the address/data bus. It is low during Ta and Tw/Td cycles for a read; it

is high during Ta and Tw/Td cycles for a write. DT/R# never changes state

when DEN# is asserted.

0 = Receive

1 = Transmit

LOCK#/ONCE#

I/O

S(L)

R(H)

H(Z)

P(Q)

BUS LOCK indicates that an atomic read-modify-write operation is in

progress. The LOCK# output is asserted in the first clock of an atomic

operation and deasserted in the last data transfer of the sequence. The

processor does not grant HOLDA while asserting LOCK#. This prevents

external agents from accessing memory involved in semaphore operations.

0 = Atomic Read-Modify-Write in Progress

1 = No Atomic Read-Modify-Write in Progress

ONCE MODE: The processor samples the ONCE input during reset. When

ONCE# is asserted LOW at the end of reset, the processor enters ONCE

mode, stops all clocks and floats all output signals. LOCK#/ONCE# has a

weak internal pullup which is active during reset to ensure normal operation

when the signal is not connected.

0 = ONCE Mode Enabled

1 = ONCE Mode Not Enabled

LRDYRCV#

R(1)

H(Q)

P(Q)

LOCAL READY/RECOVER, generated by the 80960Rx’s memory controller

unit, is an output version of the READY/RECOVER (RDYRCV#) signal.

Refer to the RDYRCV# signal description.

Table 4. Signal Descriptions (Sheet 3 of 5)

NAME

TYPE

DESCRIPTION

I960 Datasheet(PDF) 17 Page - Intel Corporation

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