DS26401 datasheet(228/309 Pages) DALLAS

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DS26401 Octal T1/E1/J1 Framer

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11.9 Per-Channel Loopback

The Per-Channel Loopback Registers (PCLRs) determine which channels (if any) from the backplane should be

replaced with the data from the receive side or in other words, off of the T1 or E1 line. If this loopback is enabled,

then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be

to tie RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or

on how many channels can be looped back.

Each of the bit position in the Per-Channel Loopback Registers (PCLR1/PCLR2/PCLR3/PCLR4) represent a time

slot in the outgoing frame. When these bits are set to a one, data from the corresponding receive channel will

replace the data on TSER for that channel.

PCL1, PCL2, PCL3, PCL4

Per-Channel Loopback Enable Registers

1D0h, 1D1h, 1D2h, 1D3h [+ (200h x n) : where n = 0 to 7, for Ports 1

to 8]

(MSB)

(LSB)

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

PCL1

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

PCL2

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

PCL3

CH32

CH31

CH30

CH29

CH28

CH27

CH26

CH25

PCL4

Bits 0 to 7 / Per-Channel Loopback Enable for Channels 1 to 32 (CH1 to CH32)

0 = Loopback disabled

1 = Enable Loopback. Source data from the corresponding receive channel

DS26401 Datasheet(PDF) 228 Page - Dallas Semiconductor

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