DS26401 datasheet(230/309 Pages) DALLAS

230 / 309 page

DS26401 Octal T1/E1/J1 Framer

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11.11 E1 Transmit Signaling Operation

There are two methods to provide transmit signaling data—processor-based (i.e., software-based) or hardware-

based. Processor-based refers to access through the transmit signaling registers, TS1-TS16, while hardware-based

refers to using the TSIG pins. Both methods can be used simultaneously.

11.11.1 Processor-Based Mode

In processor-based mode, signaling data is loaded into the Transmit Signaling registers (TS1–TS16) via the host

interface. On multiframe boundaries, the contents of these registers are loaded into a shift register for placement in

the appropriate bit position in the outgoing data stream. The user can utilize the Transmit Multiframe Interrupt in

Latched Status Register 1 (TLS1.2) to know when to update the signaling bits. The user need not update any

transmit signaling register for which there is no change of state for that register.

Each Transmit Signaling Register contains the TS16 CAS signaling (E1) for one time slot that will be inserted into

the outgoing stream if enabled to do so via TCR1.6. Signaling data can be sourced from the TS registers on a per-

channel basis by utilizing the Software Signaling Insertion Enable registers, SSIE1 through SSIE4.

In E1 mode, TS16 carries the signaling information. This information can be in either CCS (Common Channel

Signaling) or CAS (Channel Associated Signaling) format. The 32 time slots are referenced by two different channel

number schemes in E1. In “Channel” numbering, TS0 through TS31 are labeled channels 1 through 32. In “Phone

Channel” numbering TS1 through TS15 are labeled channel 1 through channel 15 and TS17 through TS31 are

labeled channel 15 through channel 30.

Time Slot Numbering Schemes

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Phone

Channel

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

11.11.2 Hardware-Based Mode

In Hardware-Based mode, signaling data is input via the TSIG pin. This signaling PCM stream is buffered and

inserted to the data stream being input at the TSER pin.

Signaling data may be input via the Transmit Hardware Signaling Channel Select (THSCS) function, the framer can

be set up to take the signaling data presented at the TSIG pin and insert the signaling data into the PCM data

stream that is being input at the TSER pin. The user has the ability to control which channels are to have signaling

data from the TSIG pin inserted into them on a per-channel basis. The signaling insertion capabilities of the framer

are available whether the transmit side elastic store is enabled or disabled. If the elastic store is enabled, the

backplane clock (TSYSCLK) can be 2.048MHz. If IBO mode is enabled then TSYSCLK may also be 4.096MHz,

8.192MHz, or 16.384MHz.

DS26401 Datasheet(PDF) 230 Page - Dallas Semiconductor