DS26401 datasheet(263/309 Pages) DALLAS

263 / 309 page

DS26401 Octal T1/E1/J1 Framer

263

12.2 BERT Description and Operation

The DS26401 contains a full-feature BERT (bit error-rate tester) that can be enabled for use with any T1/E1 port of

the device. The on-chip BERT can generate and detect both pseudorandom and repeating bit patterns.

The BERT block can generate and detect the following patterns:

Maximal-length pseudorandom patterns up to 2

32 - 1

Repetitive patterns in any length up to 512 octets

QRSS pattern per T1.403

The BERT function is assigned on a per-channel basis for both the transmitter and receiver. This is accomplished

by using the BERT expansion port control and channel select registers within the DS26401. Using this function, the

BERT pattern can be transmitted and/or received in single or across multiple DS0s, contiguous or broken. Transmit

and receive bandwidth assignments are independent of each other. The BERT resource is shared between the

eight framers of the DS26401, and the BERT transmitter and receiver can be independently assigned to different

ports of the octal framer if desired.

BSR contains the status information on the BERT function. The host can be alerted when there is a change of state

of the BERT via this register. A major change of state is defined as either a change in the receive synchronization

(i.e., the BERT has gone into or out of receive synchronization), a bit error has been detected, or an overflow has

occurred in either the Bit Counter or the Error Counter. The host must read the BERT Status Register (BSR) to

determine the change of state.

DS26401 Datasheet(PDF) 263 Page - Dallas Semiconductor