DS26401 datasheet(265/309 Pages) DALLAS

265 / 309 page

DS26401 Octal T1/E1/J1 Framer

265

12.4 Pattern Synchronization

12.4.1 Synchronization

The receiver synchronizes to the same pattern that is being transmitted. The pattern must be error-free when the

synchronizer is on line.

12.4.1.1 Polynomial Synchronization

Synchronization to polynomial patterns takes 50 + n clock cycles, where n is the exponent in the polynomial that

describes the pattern. Once synchronized, any bit that does not match the polynomial is counted as a bit error.

12.4.1.2 Repetitive Pattern Synchronization

Synchronization to repetitive patterns can take several complete repetitions of the entire pattern. The actual sync

time depends on the nature of the pattern and the location of the synchronization pointer. Errors that occur during

synchronization could affect the sync time; at least one complete error-free repetition must be received before

synchronization is declared. Once synchronized, any bit that does not match the pattern that is programmed in the

on-board RAM is counted as a bit error.

12.5 BER Calculation

12.5.1 Counters

The bit counter is active at all times. Once synchronized, the error counters come on line. The receiver has large

48-bit count registers. These counters accumulate for 50,640 hours at the T1 line rate, 1.544MHz, and 38,170

hours at the E1 line rate, 2.048MHz.

To accumulate BER data, the user toggles the LC bit at T = 0. This clears the accumulators and loads the contents

into the count registers. At T = 0, these results should be ignored. At this point, the device is counting bits and bit

errors. At the end of the specified time interval, the user toggles the LC bit again and reads the count registers.

These are the valid results used to calculate a bit-error rate.

12.6 Error Generation

The BERT can insert bit errors at a particular rate by setting the error insertion bits in Control Register 2. Injecting

errors allows users to stress communication links and to check the functionality of error monitoring equipment along

the path. In addition, the device can insert errors on command by setting the SBE bit in Control Register 2. The bit

that occurs after the rising edge of the SBE insert bit is inverted. In the case of the QRSS pattern, this could result in

a string of zeros longer than 14 bits; the DS26104 delays the erred bit by one clock cycle.

DS26401 Datasheet(PDF) 265 Page - Dallas Semiconductor