DS26401 datasheet(267/309 Pages) DALLAS

267 / 309 page

DS26401 Octal T1/E1/J1 Framer

267

12.7 BERT Control Registers

BCR1

BERT Control Register 1

2F0h

Bit #

Name

BSYNCE

BRESYNC

LPBK

QRSS

LSB

Default

Bit 0 / Transmit Load (TL).

A rising edge causes the transmit shift register to be loaded with the seed value.

Bit 1 / LSB/MSB (LSB)

0 = Repetitive Pattern data is transmitted/received MSB first.

1 = Repetitive Pattern data is transmitted/received LSB first.

Bit 2 / Pattern Select (PS)

0 = Pseudorandom pattern.

1 = Repetitive pattern.

Bit 3 / Zero Suppression Select (QRSS).

Forces a 1 into the pattern whenever the next 14 bit positions are all 0s.

Should only be set when using the QRSS pattern.

0 = Disable 14 zero suppression.

1 = Enable 14 zero suppression per T1.403.

Bit 4 / Transmit/Receive Loopback Select (LPBK)

0 = Loop back disabled.

1 = Loop back enabled.

Bit 5 / Latch Count Registers (LC).

A rising edge copies the bit count and bit error count accumulators to the

appropriate registers. The accumulators are then cleared.

Bit 6 / Initiate Manual Resync Process (BRESYNC).

A rising edge causes the device to go out of sync and begin

resynchronization process.

Bit 7 / BERT SYNC Enable (BSYNCE)

0 = Auto resync enabled.

1 = Auto resync disabled.

DS26401 Datasheet(PDF) 267 Page - Dallas Semiconductor