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ADSP-21364SBBCZENG Datasheet(PDF) 25 Page - Analog Devices

Part # ADSP-21364SBBCZENG
Description  SHARC Processor
PDF  52 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-21364SBBCZENG Datasheet(HTML) 25 Page - Analog Devices

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ADSP-21364
Preliminary Technical Data
Rev. PrB
|
Page 25 of 52
|
September 2004
Memory Read—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the
ADSP-21364 is accessing external memory space.
Table 20. 8-Bit Memory Read Cycle
Parameter
Min
Max
Unit
Timing Requirements
tDRS
Address/Data 7–0 Setup Before RD High
3.3
ns
tDRH
Address/Data 7–0 Hold After RD High
0
ns
tDAD
Address 15–8 to Data Valid
D + tPCLK – 5
ns
Switching Characteristics
tALEW
ALE Pulse Width
2 × tPCLK – 2.0
ns
tADAS
1
Address/Data 15–0 Setup Before ALE Deasserted
tPCLK – 2.5
ns
tRRH
Delay Between RD Rising Edge to Next Falling Edge.
H + tPCLK – 1
ns
tALERW
ALE Deasserted to Read Asserted
2 × tPCLK – 2
ns
tRWALE
Read Deasserted to ALE Asserted
F + H + 0.5
ns
tADAH
1
Address/Data 15–0 Hold After ALE Deasserted
tPCLK – 0.8
tALEHZ
1
ALE Deasserted to Address/Data7–0 in High Z
tPCLK – 0.8
tPCLK
ns
tRW
RD Pulse Width
D – 2
ns
tRDDRV
RD Address Drive After Read High
F + H + tPCLK – 1
ns
tADRH
Address/Data 15–8 Hold After RD High
H
ns
D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × tPCLK
H = tPCLK (if a hold cycle is specified, else H = 0)
F = 7 x tPCLK (if FLASH_MODE is set else F = 0)
tPCLK = (Peripheral) Clock Period = 2 × tCCLK
1 On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
Figure 17. Read Cycle For 8-Bit Memory Timing
VALID ADDRESS
VALID
ADDRESS
AD15-8
t
ADAS
VALID ADDRESS
AD7-0
t
ALEW
ALE
RD
tRW
WR
t
ADAH
t
ADRH
t
DRS
t
DRH
t
DAD
t
ALERW
tRWALE
VALID
DATA
VALID
ADDRESS
tRDDRV
t
ALEHZ
VALID ADDRESS
VALID ADDRESS
VALID
DATA
t
RRH



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