ADSP-21364SBBCZENG datasheet(23/52 Pages) AD

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ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 23 of 52

September 2004

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the Precision Clock Generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is not timing data available. All Timing

Parameters and Switching Characteristics apply to external DAI

pins (DAI_P07 – DAI_P20).

Table 18. Precision Clock Generator (Direct Pin Routing)

Parameter

Min

Max

Unit

Timing Requirements

tPCGIW

Input Clock Period

tSTRIG

PCG Trigger Setup Before Falling Edge of PCG Input Clock

tHTRIG

PCG Trigger Hold After Falling Edge of PCG Input Clock

Switching Characteristics

tDPCGIO

PCG Output Clock and Frame Sync Active Edge Delay After PCG

Input Clock

2.5

tDTRIG

PCG Output Clock and Frame Sync Delay After PCG Trigger

2.5 + 2.5 × tPCGOW

10 + 2.5 × tPCGOW ns

tPCGOW

Output Clock Period

Figure 15. Precision Clock Generator (Direct Pin Routing)

DAI_PN

PCG_TRIGX_I

tSTRIG

DAI_PM

PCG_EXTX_I

(CLKIN)

DAI_PY

PCG_CLKX_O

DAI_PZ

PCG_FSX_O

tHTRIG

tDPCGIO

tDTRIG

tPCGIW

tPCGOW

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